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W83627SF WINBOND I/O
W83627SF Data Sheet Revision History
Pages 1 2 3 4 5 6 7 8 9 10 n.a. All Dates 2000/09/17 2000/11/15 Version 0.50 0.60 Version on Web Main Contents First published New composition
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
W83627SF
PRELIM INARY
TABLE OF CONTENTS
GENERAL DESCRIPTION ---------------------------------------------------------------------------------- 1 PIN CONFIGURATION FOR W83627SF---------------------------------------------------------------- 6
1. PIN DESCRIPTION------------------------------------------------------------------------------------------------------------------------- 7 1.1 LPC INTERFACE -------------------------------------------------------------------------------------------------------------------------- 7 1.2 FDC INTERFACE-------------------------------------------------------------------------------------------------------------------------- 8 1.3 MULTI-MODE PARALLEL PORT ---------------------------------------------------------------------------------------------------- 9 1.4 SERIAL PORT INTERFACE ------------------------------------------------------------------------------------------------------------ 13 1.5 KBC INTERFACE-------------------------------------------------------------------------------------------------------------------------- 15 1.6 ACPI INTERFACE------------------------------------------------------------------------------------------------------------------------- 15 1.7 GAME PORT & MIDI PORT------------------------------------------------------------------------------------------------------------ 16 1.8 GENERAL PURPOSE I/O PORT-------------------------------------------------------------------------------------------------------- 17 1.8.1 General Purpose I/O Port 1 (Power source is Vcc)------------------------------------------------------------------------ 17 1.8.2 General Purpose I/O Port 2 (Power source is Vcc)------------------------------------------------------------------------ 17 1.8.3 General Purpose I/O Port 3 (Power souce is VSB) ------------------------------------------------------------------------ 18 1.9 SMART CARD INTERFACE AND GENERAL PURPOSE I/O PORT 7 (POWERED BY VCC EXCEPT SCPSNT# WHICH IS POWERED BY VSB)---------------------------------------------------------------------------------------------- 19 1.10 GENERAL PURPOSE I/O PORT 4 (POWERED BY GP4PWR) ---------------------------------------------------------------- 20 1.11 GENERAL PURPOSE I/O PORT 5, 6 (POWERED BY VCC)-------------------------------------------------------------------- 20 1.12 32KHZ CRYSTAL OSCILLATOR---------------------------------------------------------------------------------------------------- 21 1.13 POWER PINS------------------------------------------------------------------------------------------------------------------------------ 21
2. LPC (LOW PIN COUNT) INTERFACE---------------------------------------------------------------- 22 3. FDC FUNCTIONAL DESCRIPTION ------------------------------------------------------------------ 23
3.1 W83627SF FDC----------------------------------------------------------------------------------------------------------------------------- 23 3.1.1 AT interface--------------------------------------------------------------------------------------------------------------------------- 23 3.1.2 FIFO (Data) -------------------------------------------------------------------------------------------------------------------------- 23 3.1.3 Data Separator ---------------------------------------------------------------------------------------------------------------------- 24 Publication Release Date: Nov. 2000 Preliminary Revision 0.60
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W83627SF
PRELIM INARY
3.1.4 Write Precompensation------------------------------------------------------------------------------------------------------------ 25 3.1.5 Perpendicular Recording Mode ------------------------------------------------------------------------------------------------ 25 3.1.6 FDC Core ----------------------------------------------------------------------------------------------------------------------------- 25 3.1.7 FDC Commands--------------------------------------------------------------------------------------------------------------------- 25 3.2 REGISTER DESCRIPTIONS------------------------------------------------------------------------------------------------------------- 36 3.2.1 Status Register A (SA Register) (Read base address + 0) --------------------------------------------------------------- 36 3.2.2 Status Register B (SB Register) (Read base address + 1) --------------------------------------------------------------- 38 3.2.3 Digital Output Register (DO Register) (Write base address + 2) ----------------------------------------------------- 40 3.2.4 Tape Drive Register (TD Register) (Read base address + 3) ----------------------------------------------------------- 40 3.2.5 Main Status Register (MS Register) (Read base address + 4) --------------------------------------------------------- 41 3.2.6 Data Rate Register (DR Register) (Write base address + 4)------------------------------------------------------------ 41 3.2.7 FIFO Register (R/W base address + 5)---------------------------------------------------------------------------------------- 43 3.2.8 Digital Input Register (DI Register) (Read base address + 7) --------------------------------------------------------- 45 3.2.9 Configuration Control Register (CC Register) (Write base address + 7) ------------------------------------------ 46
4. UART PORT--------------------------------------------------------------------------------------------------- 47
4.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B) ------------------------------------ 47 4.2 REGISTER ADDRESS -------------------------------------------------------------------------------------------------------------------- 47 4.2.1 UART Control Register (UCR) (Read/Write)-------------------------------------------------------------------------------- 47 4.2.2 UART Status Register (USR) (Read/Write) ---------------------------------------------------------------------------------- 50 4.2.3 Handshake Control Register (HCR) (Read/Write) ------------------------------------------------------------------------ 51 4.2.4 Handshake Status Register (HSR) (Read/Write)--------------------------------------------------------------------------- 52 4.2.5 UART FIFO Control Register (UFR) (Write only) ------------------------------------------------------------------------- 53 4.2.6 Interrupt Status Register (ISR) (Read only)--------------------------------------------------------------------------------- 54 4.2.7 Interrupt Control Register (ICR) (Read/Write)----------------------------------------------------------------------------- 55 4.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) -------------------------------------------------------------- 55 4.2.9 User-defined Register (UDR) (Read/Write)---------------------------------------------------------------------------------- 56
5. CIR RECEIVER PORT------------------------------------------------------------------------------------- 57
5.1 CIR REGISTERS---------------------------------------------------------------------------------------------------------------------------- 57 5.1.1 Bank0.Reg0 - Receiver Buffer Registers (RBR) (Read)------------------------------------------------------------------- 57 5.1.2 Bank0.Reg1 - Interrupt Control Register (ICR) ---------------------------------------------------------------------------- 57 5.1.3 Bank0.Reg2 - Interrupt Status Register (ISR)------------------------------------------------------------------------------- 57 5.1.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) --------------------- 58 5.1.5 Bank0.Reg4 - CIR Control Register (CTR) ---------------------------------------------------------------------------------- 58 5.1.6 Bank0.Reg5 - UART Line Status Register (USR) -------------------------------------------------------------------------- 59 5.1.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG) ------------------------------------------------------------ 60 Publication Release Date: Nov. 2000 Revision 0.60
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W83627SF
PRELIM INARY
5.1.8 Bank0.Reg7 - User Defined Register (UDR/AUDR) ----------------------------------------------------------------------- 61 5.1.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) ------------------------------------------------------------------- 62 5.1.10 Bank1.Reg2 - Version ID Regiister I (VID)--------------------------------------------------------------------------------- 63 5.1.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3)-------------------- 63 5.1.12 Bank1.Reg4 - Timer Low Byte Register (TMRL) -------------------------------------------------------------------------- 63 5.1.13 Bank1.Reg5 - Timer High Byte Register (TMRH) ------------------------------------------------------------------------ 63
6. PARALLEL PORT ------------------------------------------------------------------------------------------ 64
6.1 PRINTER INTERFACE LOGIC --------------------------------------------------------------------------------------------------------- 64 6.2 ENHANCED PARALLEL PORT (EPP) ----------------------------------------------------------------------------------------------- 65 6.2.1 Data Swapper------------------------------------------------------------------------------------------------------------------------ 66 6.2.2 Printer Status Buffer---------------------------------------------------------------------------------------------------------------- 66 6.2.3 Printer Control Latch and Printer Control Swapper--------------------------------------------------------------------- 67 6.2.4 EPP Address Port ------------------------------------------------------------------------------------------------------------------- 67 6.2.5 EPP Data Port 0-3 ------------------------------------------------------------------------------------------------------------------ 68 6.2.6 Bit Map of Parallel Port and EPP Registers -------------------------------------------------------------------------------- 68 6.2.7 EPP Pin Descriptions-------------------------------------------------------------------------------------------------------------- 69 6.2.8 EPP Operation----------------------------------------------------------------------------------------------------------------------- 69 6.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT -------------------------------------------------------------------------- 70 6.3.1 ECP Register and Mode Definitions------------------------------------------------------------------------------------------- 70 6.3.2 Data and ecpAFifo Port----------------------------------------------------------------------------------------------------------- 71 6.3.3 Device Status Register (DSR)---------------------------------------------------------------------------------------------------- 71 6.3.4 Device Control Register (DCR) ------------------------------------------------------------------------------------------------- 72 6.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 ------------------------------------------------------------------------------ 73 6.3.6 ecpDFifo (ECP Data FIFO) Mode = 011 ------------------------------------------------------------------------------------ 73 6.3.7 tFifo (Test FIFO Mode) Mode = 110 ------------------------------------------------------------------------------------------ 73 6.3.8 cnfgA (Configuration Register A) Mode = 111----------------------------------------------------------------------------- 73 6.3.9 cnfgB (Configuration Register B) Mode = 111----------------------------------------------------------------------------- 73 6.3.10 ecr (Extended Control Register) Mode = all ------------------------------------------------------------------------------ 74 6.3.11 Bit Map of ECP Port Registers ------------------------------------------------------------------------------------------------ 75 6.3.12 ECP Pin Descriptions------------------------------------------------------------------------------------------------------------ 76 6.3.13 ECP Operation--------------------------------------------------------------------------------------------------------------------- 77 6.3.14 FIFO Operation-------------------------------------------------------------------------------------------------------------------- 77 6.3.15 DMA Transfers --------------------------------------------------------------------------------------------------------------------- 78 6.3.16 Programmed I/O (NON-DMA) Mode----------------------------------------------------------------------------------------- 78 6.4 EXTENSION FDD MODE (EXTFDD) ------------------------------------------------------------------------------------------------ 78
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIM INARY
6.5 EXTENSION 2FDD MODE (EXT2FDD) --------------------------------------------------------------------------------------------- 79
7. KEYBOARD CONTROLLER ---------------------------------------------------------------------------- 80
7.1 OUTPUT BUFFER------------------------------------------------------------------------------------------------------------------------- 81 7.2 INPUT BUFFER ---------------------------------------------------------------------------------------------------------------------------- 81 7.3 STATUS REGISTER ---------------------------------------------------------------------------------------------------------------------- 81 7.4 COMMANDS------------------------------------------------------------------------------------------------------------------------------- 82 7.5 HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC------------------------------------------------------------ 84 7.5.1 KB Control Register (Logic Device 5, CR-F0)------------------------------------------------------------------------------ 84 7.5.2 Port 92 Control Register (Default Value = 0x24) ------------------------------------------------------------------------- 84
8. GENERAL PURPOSE I/O --------------------------------------------------------------------------------- 85 9. PLUG AND PLAY CONFIGURATION ---------------------------------------------------------------- 89
9.1 COMPATIBLE PNP ----------------------------------------------------------------------------------------------------------------------- 89 9.1.1 Extended Function Registers ---------------------------------------------------------------------------------------------------- 89 9.1.2 Extended Functions Enable Registers (EFERs) ---------------------------------------------------------------------------- 90 9.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) -------------------- 90 9.2 CONFIGURATION SEQUENCE-------------------------------------------------------------------------------------------------------- 90 9.2.1 Enter the extended function mode---------------------------------------------------------------------------------------------- 90 9.2.2 Configurate the configuration registers-------------------------------------------------------------------------------------- 91 9.2.3 Exit the extended function mode------------------------------------------------------------------------------------------------ 91 9.2.4 Software programming example ------------------------------------------------------------------------------------------------ 91
10. ACPI REGISTERS FEATURES ------------------------------------------------------------------------ 93 11. SMART CARD INTERFACE--------------------------------------------------------------------------- 94
11.1 RECEIVER BUFFER REGISTER (RBR, READ ONLY AT "BASE ADDRESS + 0" WHEN BDLAB = 0) ----------- 94 11.2 TRANSMITTER BUFFER REGISTER (TBR, WRITE ONLY AT "BASE ADDRESS + 0" WHEN BDLAB = 0)-- 94 11.3 INTERRUPT CONTROL REGISTER (ICR, AT "BASE ADDRESS + 1" WHEN BDLAB = 0)------------------------- 94 11.4 INTERRUPT STATUS REGISTER (ISR, REA D ONLY AT "BASE ADDRESS + 2")----------------------------------- 95 11.5 SMART CARD FIFO CONTROL REGISTER (SCFR, WRITE ONLY AT "BASE ADDRESS + 2") ----------------- 96 11.6 SMART CARD CONTROL REGISTER (SCCR, WRITE ONLY AT "BASE ADDRESS + 3")------------------------- 97 11.7 INTERRUPT ENABLE REGISTER (IER, AT "BASE ADDRESS + 4")------------------------------------------------------ 97 11.8 SMART CARD STATUS REGISTER (SCSR, AT "BASE ADDRESS + 5")----------------------------------------------- 98 11.9 EXTENDED CONTROL REGISTER (ECR, AT "BASE ADDRESS + 7")--------------------------------------------------- 99
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W83627SF
PRELIM INARY
11.10 BAUD RATE DIVISOR LATCH HIGH AND BAUD RATE DIVISOR LATCH LOW (BHL AND BLL AT "BASE ADDRESS + 1" AND "BASE ADDRESS + 0" RESPECTIVELY WHEN BDLAB = 1) ----------------------------- 100
12. SERIAL IRQ------------------------------------------------------------------------------------------------- 102
12.1 START FRAME-------------------------------------------------------------------------------------------------------------------------- 102 12.2 IRQ/DATA FRAME--------------------------------------------------------------------------------------------------------------------- 102 12.3 STOP FRAME----------------------------------------------------------------------------------------------------------------------------- 103
13. CONFIGURATION REGISTER ----------------------------------------------------------------------- 104
13.1 CHIP (GLOBAL) CONTROL REGISTER-------------------------------------------------------------------------------------------- 104 13.2 LOGICAL DEVICE 0 (FDC) ------------------------------------------------------------------------------------------------------------ 110 13.3 LOGICAL DEVICE 1 (PARALLEL PORT)------------------------------------------------------------------------------------------ 114 13.4 LOGICAL DEVICE 2 (UART A) ------------------------------------------------------------------------------------------------------ 115 13.5 LOGICAL DEVICE 3 (UART B)------------------------------------------------------------------------------------------------------- 115 13.6 LOGICAL DEVICE 5 (KBC) ------------------------------------------------------------------------------------------------------------ 117 13.7 LOGICAL DEVICE 6 (CIR) ------------------------------------------------------------------------------------------------------------- 118 13.8 LOGICAL DEVICE 7 (GAME PORT AND MIDI PORT AND GPIO PORT 1)--------------------------------------------- 119 13.9 LOGICAL DEVICE 8 (GPIO PORT 2) ------------------------------------------------------------------------------------------------ 120 13.10 LOGICAL DEVICE 9 (GPIO PORT 3,4 ARE POWERED BY STANDBY SOURCE VSB) ------------------------------ 122 13.11 LOGICAL DEVICE A (ACPI)--------------------------------------------------------------------------------------------------------- 123 13.12 LOGICAL DEVICE B (SMART CARD INTERFACE) -------------------------------------------------------------------------- 131 13.13 LOGICAL DEVICE C (GPIO PORT 5,6,7 THIS POWER OF THE PORTS IS SOURCE VCC) ------------------------- 131
14. SPECIFICATIONS ----------------------------------------------------------------------------------------- 134
14.1 ABSOLUTE MAXIMUM RATINGS ------------------------------------------------------------------------------------------------ 134 14.2 DC CHARACTERISTICS--------------------------------------------------------------------------------------------------------------- 134
15. APPLICATION CIRCUITS ------------------------------------------------------------------------------ 137
15.1 PARALLEL PORT EXTENSION FDD----------------------------------------------------------------------------------------------- 137 15.2 PARALLEL PORT EXTENSION 2FDD --------------------------------------------------------------------------------------------- 138 15.3 FOUR FDD MODE----------------------------------------------------------------------------------------------------------------------- 138
16. ORDERING INSTRUCTION--------------------------------------------------------------------------- 139 17. HOW TO READ THE TOP MARKING ------------------------------------------------------------- 139 18. PACKAGE DIMENSIONS------------------------------------------------------------------------------- 140
Publication Release Date: Nov. 2000 Revision 0.60
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W83627SF PRELIMINARY
GENERAL DESCRIPTION
The W83627SF is the new generation of Winbond's LPC I/O products. It features a whole new interface, namely LPC (Low Pin Count) interface, which is supported in mainstream Intel chip-set. This interface as its name suggests is to provide an economical implementation of I/O's interface with lower pin count and still maintains equivalent performance as its ISA interface counterpart. Approximately 40 pins are saved in LPC I/O comparing to ISA implementation. With this additional freedom, we can implement more devices on a single chip as demonstrated in W83627SF's integration of Game Port and MIDI Port. It is fully transparent in terms of software which means no BIOS or device driver update is needed except chip-specific configuration. As Smart Card application is gaining more and more attention, W83627SF also implements a smart card reader interface featuring Smart wake-up function. This smart card reader interface fully meets the ISO7816 and PC/SC (Personal Computer/Smart Card Workgroup) standards. W83627SF provides a minimum external components and lowest cost soultion for smart card applications. The disk drive adapter functions of W83627SF include a floppy disk drive controller compatible with the industry standard 82077/765, data s eparator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of functions integrated onto the W83627SF greatly reduces the number of components required for interfacing with floppy disk drives. The W83627SF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s. The W83627SF provides two high-speed serial communication p orts (UARTs), one of which supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability, and a processor interrupt system. Both UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud rates of 230k, 460k, or 921k bps which support higher speed modems. In addition, the W83627SF provides IR functions: IrDA 1.0 (SIR for 1.152K bps) and TV remote IR ( onsumer IR, supporting NEC, RC-5, C extended RC-5, and RECS-80 protocols).
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
The W83627SF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or two external floppy disk drives to be connected. The configuration registers support mode selection, function enable/disable, and power down function selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature
TM
demand of Windows 95/98
, which makes system resource allocation more efficient than ever.
The W83627SF provides functions that complies with ACPI (Advanced Configuration and Power Interface), which includes support of legacy and ACPI power management through PME# or PSOUT# function pins. For OnNow keyboard Wake-Up, OnNow mouse Wake-Up, and OnNow CIR Wake-Up. The W83627SF also has auto power management to reduce the power consumption. The keyboard controller is based on 8042 compatible instruction set with a 2K Byte programmable ROM and a 256-Byte RAM bank. Keyboard BIOS firmware are available with optional AMIKEY MultiKey/42
TM TM -2, Phoenix
, or customer code.
The W83627SF provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a predefined alternate function. The W83627SF is made to fully comply with Microsoft PC98 and PC99 Hardware Design Guide. Moreover, W83627SF is made to meet the specification of PC2000/PC2001's requirement in the power management: ACPI and DPM (Device Power Management). The W83627SF contains a game port and a MIDI port. The game port is designed to support 2 joysticks and can be applied to all standard PC game control devices. They are very important for a entertainment or consumer computer.
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY FEATURES
General
* * * * * * Meet LPC Spec. 1.01 Support LDRQ#(LPC DMA), SERIRQ (serial IRQ) Compliant with Microsoft PC2000/PC2001 Hardware Design Guide Support DPM (Device Power Management), ACPI Programmable configuration settings Single 24 or 48 MHz clock input
FDC
* * * * * * * * * * * * * Compatible with IBM PC AT disk drive systems Variable write pre-compensation with track selectable capability Support vertical recording format DMA enable logic 16-byte data FIFOs Support floppy disk drives and tape drives Detects all overrun and underrun conditions Built-in address mark detection circuit to simplify the read electronics FDD anti-virus functions with software write protect and FDD write enable signal (write data signal was forced to be inactive) Support up to four 3.5-inch or 5.25-inch floppy disk drives Completely compatible with industry standard 82077 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate Support 3-mode FDD, and its Win95/98 driver
UART
* * * Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs MIDI compatible Fully programmable serial-interface characteristics: --- 5, 6, 7 or 8-bit characters --- Even, odd or no parity bit generation/detection
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
--- 1, 1.5 or 2 stop bits generation * Internal diagnostic capabilities: --- Loop-back controls for communications link fault isolation --- Break, parity, overrun, framing error simulation * * Programmable baud generator allows division of 1.8461 MHz and 24 MHz by 1 to (216-1) Maximum baud rate up to 921k bps for 14.769 MHz and 1.5M bps for 24 MHz
Infrared
* * * Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps Support Consumer IR
Parallel Port
* * * * * * Compatible with IBM parallel port Support PS/2 compatible bi-directional parallel port Support Enhanced Parallel Port (EPP) - Compatible with IEEE 1284 specification Support Extended Capabilities Port (ECP) - Compatible with IEEE 1284 specification Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and B through parallel port Enhanced printer port back-drive current protection
Keyboard Controller
* * * * * * * * * 8042 based with optional F/W from AMIKKEY
TM
-2, Phoenix MultiKey/42
TM
or customer code
with 2K bytes of programmable ROM, and 256 bytes of RAM Asynchronous Access to Two Data Registers and One status Register Software compatibility with the 8042 Support PS/2 mouse Support port 92 Support both interrupt and polling modes Fast Gate A20 and Hardware Keyboard Reset 8 Bit Timer/ Counter Support binary and BCD arithmetic
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
* 6 MHz, 8 MHz, 12 MHz, or 16 MHz operating frequency
Game Port
* * Support two separate Joysticks Support every Joystick two axis (X,Y) and two button (A,B) controllers
MIDI Port
* * * The baud rate is 31.25 Kbaud 16-byte input FIFO 16-byte output FIFO
General Purpose I/O Ports
* * 40 programmable general purpose I/O ports General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, ,watching dog timer output, power LED output, infrared I/O pins, KBC control I/O pins, suspend LED output, RSMRST# signal, PWROK signal, STR(suspend to DRAM) function, VID control function,
OnNow Functions
* * * * * Keyboard Wake-Up by programmable keys Mouse Wake-Up by programmable buttons CIR Wake-Up by programmable keys SMART Card Wake-up by SCPSNT On Now Wake-Up from all of the ACPI sleeping states (S1-S5)
Smart Card Reader Interface
* * * * PC/SC T=0, T=1 compliant ISO7816 protocol compliant With 16-byte send/receive FIFOs Programmable baud generator
Package
* 128-pin PQFP
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY PIN CONFIGURATION FOR W83627SF
MCLK MDATA PSOUT# PSIN CIRRX#/GP34 RSMRST#/GP33 PWROK/GP32 PWRCTL#/GP31 SLP_SX#/GP30 VBAT SUSCLKIN GP63 VCC CTSB# DSRB# RTSB#/ENGMTO DTRB# SINB SOUTB/PEN48 DCDB# RIB# VSS IRTX/GP26 IRRX/GP25 WDTO/GP24 PLED/GP23 GP22/VID14 GP21/VID13 XIN VBAT XOUT 32KOUT GP57CLK/VIDSEL GP62/VIDI2 GP61/VIDI1 GP60/VIDI0 GP4PWR GP42/STREN 1 1 1 99 9 9 9 99 9 9 9 8 8 88 8 88 8 8 8 77 7 7 77 7 7 7 7 6 6 6 6 6 0 0 0 98 7 6 5 43 2 1 0 9 8 76 5 43 2 1 0 98 7 6 54 3 2 1 0 9 8 7 6 5 21 0 S5IN#/GP41 STRCTL/GP40 GP56/PVIDLIM1 GP55/VIDO4 GP54/VIDO3 GP53/VIDO2 GP52/VIDO1 GP51/VIDO0 GP50/PVIDLIM0 SCPSNT/GP74 SCIO/GP73 VCC SCPWR/GP72/STGP72 SCCLK/GP71 VSS SCRST#/GP70/STGP70 MSI/GP20 MSO/IRQIN0 GPSA2/GP17 GPSB2/GP16 GPY1/GP15 GPY2/P16/GP14 GPX2/P15/GP13 GPX1/P14/GP12 GPSB1/P13/GP11 GPSA1/P12/GP10 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 SUSLED/GP35 KDATA KCLK VSB KBRST A20GATE KBLOCK# RIA# DCDA# VSS PENKBC/SOUTA SINA PNPCSV#/DTRA# HEFRAS/RTSA# DSRA# CTSA# VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3
W83627SF
1 1 11 1 1 1 1 1 12 2 2 2 2 22 2 2 23 33 3 3 33 33 1 2 34 5 67 8 90 1 23 4 5 6 7 8 90 1 2 3 4 56 7 8 90 12 3 4 56 78
PD4 PD5 PD6 PD7 ACK# BUSY PE SLCT LRESET# LFRAME# VCC3V LAD0 LAD1 LAD2 LAD3 SERIRQ LDRQ# PCICLK VSS PME# CLKIN DSKCHG# HEAD# RDATA# WP# TRAKD# VCC WE# WD# STEP# DIR# MOB# DSA# DSB# MOA# INDEX# DRVDEN1/IRQIN1/SMI#/GP27 DRVDEN0
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
1. PIN DESCRIPTION
Note: Please refer to Section 13.2 DC CHARACTERISTICS for details. I/O8t - TTL level bi-directional pin with 8 mA source-sink capability I/O12t - TTL level bi-directional pin with 12 mA source-sink capability I/O12tp3 - 3.3V TTL level bi-directional pin with 12 mA source-sink capability I/OD12t - TTL level bi-directional pin open drain output with 12 mA sink capability I/OD16t - TTL level bi-directional pin open drain output with 16 mA sink capability I/OD24 - TTL level bi-directional pin open drain output with 24A sink capability OUT2 - Output pin with 2 mA source-sink capability OUT12 - Output pin with 12 mA source-sink capability O12tp3 - 3.3V output pin with 12 mA source-sink capability OD12 - Open-drain output pin with 12 mA sink capability OD24 - Open-drain output pin with 24 mA sink capability INcs - CMOS level Schmitt-trigger input pin INt - TTL level input pin INtd - TTL level input pin with internal pull down resistor INts - TTL level Schmitt-trigger input pin INtsp3 - 3.3V TTL level Schmitt-trigger input pin
1.1
LPC Interface
PIN 18 I/O INt FUNCTION System clock input. According to the input frequency 24MHz or 48MHz, it is selectable through register. Default is 24MHz input.
SYMBOL CLKIN
PME# PCICLK LDRQ# SERIRQ LAD[3:0]
19 21 22 23 24-27
OD12 INtsp3 O12tp3 I/OD12t I/O12tp3
Generated PME event. PCI clock input. Encoded DMA Request signal. Serial IRQ input/Output. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral.
LFRAME# LRESET# SUSCLKIN
29 30 75
INtsp3 INtsp3 INts
Indicates start of a new cycle or termination of a broken cycle. Reset signal. It can connect to PCIRST# signal on the host. 32khz clock input , for CIR only. Publication Release Date: Nov. 2000 Revision 0.60
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W83627SF
PRELIMINARY
1.2 FDC Interface
PIN 1 2 I/O OD24 OD12 OD12 INt I/OD12t 3 INcs FUNCTION Drive Density Select bit 0. Drive Density Select bit 1. (Default) System Management Interrupt. Interrupt channel input. General purpose I/O port 2 bit 7. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Motor A On. When set to 0, this pin enables disk drive 0. This is an open drain output. Drive Select B. When set to 0, this pin enables disk drive B. This is an open drain output. Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output. Motor B On. When set to 0, this pin enables disk drive 1. This is an open drain output. Direction of the head step motor. An open drain output. Logic 1 = outward motion Logic 0 = inward motion Step output pulses. This active low open drain output produces a pulse to move the head to another track. Write data. This logic low open drain writes pre-compensation serial data to the selected FDD. An open drain output. Write enable. An open drain output. Track 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
SYMBOL DRVDEN0 DRVDEN1 SMI# IRQIN1 GP27 INDEX#
MOA# DSB# DSA# MOB# DIR#
4 5 6 7 8
OD24 OD24 OD24 OD24 OD24
STEP# WD# WE# TRAK0#
9 10 11 13
OD24 OD24 OD24 INcs
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
1.2 FDC Interface, continued
SYMBOL WP#
PIN 14
I/O INcs
FUNCTION Write protected. This active low Schmitt input from the disk drive indicates that the diskette is write-protected. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
RDATA#
15
INcs
The read data input signal from the FDD. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1 Diskette change. This signal is active low at power on and whenever the diskette is removed. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
HEAD#
16
OD24
DSKCHG#
17
INcs
1.3
Multi-Mode Parallel Port
PIN 31 I/O INt FUNCTION PRINTER MODE: An active high input on this pin indicates that the printer is selected. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WE2# This pin is for Extension FDD B; its function is the same as the WE# pin of FDC. EXTENSION 2FDD MODE: WE2# This pin is for Extension FDD A and B; its function is the same as the WE# pin of FDC. PRINTER MODE: An active high input on this pin indicates that the printer has detected the end of the paper. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WD2# This pin is for Extension FDD B; its function is the same as the WD# pin of FDC. EXTENSION 2FDD MODE: WD2# This pin is for Extension FDD A and B; its function is the same as the WD# pin of FDC.
SYMBOL SLCT
OD12
OD12
PE
32
INt
OD12
OD12
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
1.3 Multi-Mode Parallel Port, continued
SYMBOL BUSY
PIN 33
I/O INt
OD12
FUNCTION PRINTER MODE: An active high input indicates that the printer is not ready to receive data. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: MOB2# This pin is for Extension FDD B; its function is the same as the MOB# pin of FDC. EXTENSION 2FDD MODE: MOB2# This pin is for Extension FDD A and B; its function is the same as the MOB# pin of FDC. PRINTER MODE: ACK# An active low input on this pin indicates that the printer has received data and is ready to accept more data. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DSB2# This pin is for the Extension FDD B; its functions is the same as the DSB# pin of FDC. EXTENSION 2FDD MODE: DSB2# This pin is for Extension FDD A and B; its function is the same as the DSB# pin of FDC. PRINTER MODE: PD7 Parallel port data bus bit 7. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: DSA2# This pin is for Extension FDD A; its function is the same as the DSA# pin of FDC. PRINTER MODE: PD6 Parallel port data bus bit 6. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION. 2FDD MODE: MOA2# This pin is for Extension FDD A; its function is the same as the MOA# pin of FDC. PRINTER MODE: PD5 Parallel port data bus bit 5. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output.
OD12
ACK#
34
INt
OD12
OD12
PD7
35
I/OD12t
OD12
PD6
36
I/OD12t OD12
PD5
37
I/O12t
-
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
1.3 Multi-Mode Parallel Port, continued
SYMBOL PD4
PIN 38
I/O I/O12t
INt
INt PD3 39 I/O12t
INt
INt
PD2
40
I/O12t
INt
INt
FUNCTION PRINTER MODE: PD4 Parallel port data bus bit 4. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DSKCHG2# This pin is for Extension FDD B; the function of this pin is the same as the DSKCHG# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: DSKCHG2# This pin is for Extension FDD A and B; this function of this pin is the same as the DSKCHG# pin of FDC. It is pulled high internally. PRINTER MODE: PD3 Parallel port data bus bit 3. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: RDATA2# This pin is for Extension FDD B; its function is the same as the RDATA# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: RDATA2# This pin is for Extension FDD A and B; its function is the same as the RDATA# pin of FDC. It is pulled high internally. PRINTER MODE: PD2 Parallel port data bus bit 2. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WP2# This pin is for Extension FDD B; its function is the same as the WP# pin of FDC. It is pulled high internally. EXTENSION. 2FDD MODE: WP2# This pin is for Extension FDD A and B; its function is the same as the WP# pin of FDC. It is pulled high internally. PRINTER MODE: PD1 Parallel port data bus bit 1. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: TRAK02# This pin is for Extension FDD B; its function is the same as the TRAK0# pin of FDC. It is pulled high internally. EXTENSION. 2FDD MODE: TRAK02# This pin is for Extension FDD A and B; its function is the same as the TRAK0# pin of FDC. It is pulled high internally.
PD1
41
I/O12t
INt
INt
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
1.3 Multi-Mode Parallel Port, continued
SYMBOL PD0
PIN 42
I/O I/O12t
INt
INt
SLIN#
43
OD12
OD12
OD12 INIT# 44 OD12
OD12
OD12 ERR# 45 INt
OD12 OD12
FUNCTION PRINTER MODE: PD0 Parallel port data bus bit 0. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: INDEX2# This pin is for Extension FDD B; its function is the same as the INDEX# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: INDEX2# This pin is for Extension FDD A and B; its function is the same as the INDEX# pin of FDC. It is pulled high internally. PRINTER MODE: SLIN# Output line for detection of printer selection. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: STEP2# This pin is for Extension FDD B; its function is the same as the STEP# pin of FDC. EXTENSION 2FDD MODE: STEP2# This pin is for Extension FDD A and B; its function is the same as the STEP# pin of FDC. PRINTER MODE: INIT# Output line for the printer initialization. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DIR2# This pin is for Extension FDD B; its function is the same as the DIR# pin of FDC. EXTENSION 2FDD MODE: DIR2# This pin is for Extension FDD A and B; its function is the same as the DIR# pin of FDC. PRINTER MODE: ERR# An active low input on this pin indicates that the printer has encountered an error condition. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: HEAD2# This pin is for Extension FDD B; its function is the same as the HEAD#pin of FDC. EXTENSION 2FDD MODE: HEAD2# This pin is for Extension FDD A and B; its function is the same as the HEAD# pin of FDC.
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
1.3 Multi-Mode Parallel Port, continued
SYMBOL AFD#
PIN 46
I/O OD12
OD12
OD12 STB# 47 OD12
FUNCTION PRINTER MODE: AFD# An active low output from this pin causes the printer to auto feed a line after a line is printed. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DRVDEN0 This pin is for Extension FDD B; its function is the same as the DRVDEN0 pin of FDC. EXTENSION 2FDD MODE: DRVDEN0 This pin is for Extension FDD A and B; its function is the same as the DRVDEN0 pin of FDC. PRINTER MODE: STB# An active low output is used to latch the parallel data into the printer. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output.
-
1.4
Serial Port Interface
PIN 49 78 50 79 51 INt I/O INt FUNCTION Clear To Send. It is the modem control input. The function of these pins can be tested by reading bit 4 of the handshake status register. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. UART A Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. During power-on reset, this pin is pulled down internally and is defined as HEFRAS, which provides the power-on value for CR26 bit 6 (HEFRAS). A 4.7 k is recommended if intends to pull up. (select 4EH as configuration I/O ports address)
SYMBOL CTSA# CTSB# DSRA# DSRB# RTSA# HEFRAS
I/O8t
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
1.4 Serial Port Interface, continued
SYMBOL RTSB# ENGMTO
PIN 80
I/O I/O8t
DTRA# PNPCSV#
52
I/O8t
DTRB# SINA SINB SOUTA PENKBC
81 53 82 54
I/O8t INt I/O8t
FUNCTION UART B Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. Power on setting pin for enabling Watch Dog timer and its countdown. This pin is pulled down internally and provides the power-on value for bit 0 of CR30 and a count value of 0x0A for CRF6 in logical device 8. A 4.7 k is recommended if intends to pull up. UART A Data Terminal Ready. An active low signal informs the modem or data set that the controller is ready to communicate. During power-on reset, this pin is pulled d own internally and is defined as PNPCSV#, which provides the power-on value for CR24 bit 0 (PNPCSV#). A 4.7 k is recommended if intends to pull up. (clear the default value of FDC, UARTs, PRT, Game port and MIDI port) UART B Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. Serial Input. It is used to receive serial data through the communication link. UART A Serial Output. It is used to transmit serial data out to the communication link. During power-on reset, this pin is pulled down internally and is defined as PENKBC, which provides the power-on value for CR24 bit 2 (ENKBC). A 4.7 k resistor is recommended if intends to pull up. (enable KBC) UART B Serial Output. During power-on reset, this pin is pulled down internally and is defined as PEN48, which provides the power-on value for CR24 bit 6 (EN48). A 4.7 k resistor is recommended if intends to pull up.
SOUTB PEN48
83
I/O8t
DCDA# DCDB# RIA# RIB#
56 84 57 85
INt INt
Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set.
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W83627SF
PRELIMINARY
1.5 KBC Interface
PIN 58 59 60 62 63 65 66 I/O INt OUT12 OUT12 I/OD16t I/OD16t I/OD16t I/OD16t FUNCTION Keyboard inhibit control input. This pin is after system reset. Internal pull high. (KBC P17) Gate A20 output. This pin is high after system reset. (KBC P21) Keyboard reset. This pin is high after system reset. (KBC P20) Keyboard Clock. Keyboard Data. PS2 Mouse Clock. PS2 Mouse Data.
SYMBOL KBLOCK# A20GATE KBRST KCLK KDATA MCLK MDATA
1.6
ACPI Interface
PIN 67 68 74 I/O OD12 IN td PWR FUNCTION Panel Switch Output. This signal is used for Wake-Up system from S5cold state. This pin is pulse output, active low. Panel Switch Input. This pin is high active with an internal pull down resistor. Battery voltage input.
SYMBOL PSOUT# PSIN VBAT
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
1.7
MSI GP20 MSO IRQIN0 GPSA2 GP17 GPSB2 GP16 GPY1 GP15 GPY2 GP14 P16 GPX2 GP13 P15 125 124 123 122 120 121
Game Port & MIDI Port
PIN 119 I/O INt I/OD12t OUT12 INt INcs I/OD12t INcs I/OD12 I/OD12 I/OD12t I/OD12 I/OD12t I/OD12t I/OD12 I/OD12t I/OD12t MIDI serial data input. General purpose I/O port 2 bit 0. MIDI serial data output. (Default) Alternate Function input: Interrupt channel input. Active-low, Joystick I switch input 2. This pin has an internal pullup resistor. (Default) General purpose I/O port 1 bit 7. Active-low, Joystick II switch input 2. This pin has an internal pullup resistor. (Default) General purpose I/O port 1 bit 6. Joystick I timer pin. this pin connect to Y positioning variable resistors for the Josystick. (Default) General purpose I/O port 1 bit 5. Joystick II timer pin. this pin connect to Y positioning variable resistors for the Josystick. (Default) General purpose I/O port 1 bit 4. Alternate Function Output:KBC P16 I/O port. Joystick II timer pin. this pin connect to X positioning variable resistors for the Josystick. (Default) General purpose I/O port 1 bit 3. Alternate Function Output:KBC P15 I/O port. FUNCTION
SYMBOL
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
1.7 Game Port & MIDI Port, continued
SYMBOL GPX1 GP12 P14 GPSB1 GP11 P13 GPSA1 GP10 P12
PIN 126
I/O I/OD12 I/OD12t I/OD12t
FUNCTION Joystick I timer pin. this pin connect to X positioning variable resistors for the Josystick. (Default) General purpose I/O port 1 bit 2. Alternate Function Output:KBC P14 I/O port. Active-low, Joystick II switch input 1. (Default) General purpose I/O port 1 bit 1. Alternate Function Output:KBC P13 I/O port. Active-low, Joystick I switch input 1. (Default) General purpose I/O port 1 bit 0. Alternate Function Output:KBC P12 I/O port.
127
INcs I/OD12t I/OD12t
128
INcs I/OD12t I/OD12t
1.8
1.8.1
General Purpose I/O Port
General Purpose I/O Port 1 (Power source is Vcc) see 1.7 Game Port
1.8.2
General Purpose I/O Port 2 (Power source is Vcc) PIN 87 I/O I/OD12t OUT12 88 I/OD12t INts 89 I/OD12t OD12 90 I/OD24t OD24 91 I/OD12t INt 92 I/OD12t INt FUNCTION General purpose I/O port 2 bit 6. Alternate Function Output: Infrared Transmitter Output. (Default) General purpose I/O port 2 bit 5. Alternate Function Input: Infrared Receiver input. (Default) General purpose I/O port 2 bit 4. Watch dog timer output. (Default) General purpose I/O port 2 bit 3. Power LED output, this signal is low after system reset. (Default) General purpose I/O port 2 bit 2. Alternate VID input bit 4. General purpose I/O port 2 bit 1. Alternate VID input bit 3.
SYMBOL GP26 IRTX GP25 IRRX GP24 WDTO GP23 PLED GP22 VIDI4 GP21 VIDI3
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W83627SF
PRELIMINARY
1.8.3 General Purpose I/O Port 3 (Power souce is VSB) PIN 64 I/O I/OD24t OD24 69 I/OD12t OD12 70 I/OD12t OD12 71 I/OD12t OD12 72 I/OD12t OD12 73 I/OD12t INt FUNCTION General purpose I/O port 3 bit 5. Suspend LED output, it can program to flash when suspend state. This function can work without VCC. (Default) General purpose I/O port 3 bit 4. Consumer IR receiving input. This pin can Wake-Up system from S5cold. (Default) General purpose I/O port 3 bit 3. This pin generates the RSMRST signal while the VSB come in. (Default) General purpose I/O port 3 bit 2. This pin generates the PWROK signal while the VCC come in. (Default) General purpose I/O port 3 bit 1. This pin generates the PWRCTL# signal while the power failure. (Default) General purpose I/O port 3 bit 0. Chpset suspend C status input. SYMBOL GP35 SUSLED GP34 CIRRX# GP33 RSMRST# GP32 PWROK GP31 PWRCTL# GP30 SLP_SX#
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
1.9 SMART CARD Interface and General Purpose I/O port 7 (Powered by VCC except SCPSNT# which is powered by VSB)
SYMBOL SCPSNT GP74 SCIO GP73 SCPWR GP72 STGP72 115 113 PIN 112 I/O INts I/O12ts I/O12t I/OD12t OUT12 I/O12t FUNCTION Smart card present detection Schmitt-trigger input. General purpose I/O port 7 bit 4. Smart card data I/O channel. General purpose I/O port 7 bit 3. Smart card power control. General purpose I/O port 7 bit 2. Power on setting pin for selecting functions of GP7. Setting value is latched on the rising edge of POWEROK. This pin is internally pulled down during power on, a 4.7 k resistor is recommended if intends to pull up. Refer to detailed descrption of CR2C bit 6, 5. 116 OUT12 I/O12t 118 OUT12 I/O12t Smart card clock output. General purpose I/O port 7 bit 1. Smart card reset output. General purpose I/O port 7 bit 0. Power on setting pin for selecting functions of GP7. Setting value is latched on the rising edge of POWEROK. This pin is internally pulled down during power on, a 4.7 k resistor is recommended if intends to pull up. Refer to detailed descrption of CR2C bit 6, 5.
SCCLK GP71 SCRST# GP70 STGP70
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
1.10 General Purpose I/O Port 4 (Powered by GP4PWR)
PIN 101 102 I/O PWR I/O12t FUNCTION +5V stand-by power supply dedicated for GP4. General purpose I/O port 4 bit 2. Power on setting pin for selecting functions of GP4. Setting value is latched on the rising edge of RSMRST#. This pin is internally pulled down during power on, a 4.7 k resistor is recommended if intends to pull up. Refer to detailed descrption of CR29 bit 0. General purpose I/O port 4 bit 1. S5 input signal to indicate in S5 state. General purpose I/O port 4 bit 0. For suspend to ram function to control Ram power.
SYMBOL GP4PWR GP42 STREN
GP41 S5IN# GP40 STRCTL
103 104
I/O12t I/O12t
1.11
GP57
General Purpose I/O Port 5, 6 (Powered by VCC)
PIN 97 I/O I/O12t FUNCTION General purpose I/O port 5 bit 7. Power on setting pin for selecting VID function. Setting value is latched on the rising edge of POWEROK. This pin is internally pulled down during power on, a 4.7 k resistor is recommended if intends to pull up. Refer to detailed descrption of CR2C bit 7. General purpose I/O port 5 bit 6. Power on setting pin for selecting VID guarding function. Setting value is latched on the rising edge of POWEROK. This pin is internally pulled down during power on, a 4.7 k resistor is recommended if intends to pull up. Refer to detailed descrption of bit 6 of CRFA in logical device C. General purpose I/O port 5 bit 5. Alternate VID output bit 4. General purpose I/O port 5 bit 4. Alternate VID output bit 3. General purpose I/O port 5 bit 3. Alternate VID output bit 2.
SYMBOL VIDSEL
GP56 PVIDLIM1
105
I/O12t
GP55 VIDO4 GP54 VIDO3 GP53 VIDO2
106
I/OD12t OD12
107
I/OD12t OD12
108
I/OD12t OD12
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
1.11 General Purpose I/O Port 5, 6 (Powered by VCC), continued
SYMBOL GP52 VIDO1 GP51 VIDO0 GP50 PVIDLIM0
PIN 109
I/O I/OD12t OD12 Alternate VID output bit 1.
FUNCTION General purpose I/O port 5 bit 2.
110
I/OD12t OD12
General purpose I/O port 5 bit 1. Alternate VID output bit 0. General purpose I/O port 5 bit 0. Power on setting pin for selecting VID guarding function. Setting value is latched on the rising edge of POWEROK. This pin is internally pulled down during power on, a 4.7 k resistor is recommended if intends to pull up. Refer to detailed descrption of bit 5 of CRFA in logical device C. General purpose I/O port 6 bit 2. General purpose I/O port 6 bit 2. Alternate VID input bit 2. General purpose I/O port 6 bit 1. Alternate VID input bit 1. General purpose I/O port 6 bit 0. Alternate VID input bit 0.
111
I/O12t
GP63 GP62 VIDI2 GP61 VIDI1 GP60 VIDI0
76 98 99 100
I/OD12t I/OD12t INt I/OD12t INt I/OD12t INt
1.12
XIN VBAT
32KHz crystal oscillator
PIN 93 94 95 96 I/O IN PWR OUT OUT2 Crystal input Dedicated power supply for oscillator. Crystal output 32KHz output clock. FUNCTION
SYMBOL
XOUT
CLK32KOUT
1.13
POWER PINS
PIN 28 12, 48, 77, 114 61 20, 55, 86, 117 FUNCTION +3.3V power supply for driving 3V on host interface. +5V power supply for the digital circuitry. +5V stand-by power supply for the digital circuitry. Ground.
SYMBOL VCC3V VCC VSB VSS
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY 2. LPC (LOW PIN COUNT) INTERFACE
LPC interface is to replace ISA interface serving as a bus interface between host (chip-set) and peripheral (Winbond I/O). Data transfer on the LPC bus are serialized over a 4 bit bus. The general characteristics of the interface implemented in Winbond LPC I/O are: * * * * * * * One control line, namely LFRAME#, which is used by the host to start or stop transfers. peripherals drive this signal. The LAD[3:0] bus, which communicates information serially. The information conveyed are cycle type, cycle direction, chip selection, address, data, and wait states. MR (master reset) of Winbond ISA I/O is replaced with a active low reset signal, namely LRESET#, in Winbond LPC I/O. An additional 33 MHz PCI clock is needed in Winbond LPC I/O for synchronization. DMA requests are issued through LDRQ#. Interrupt requests are issued through SERIRQ. Power management events are issued through PME#. No
Comparing to its ISA counterpart, LPC implementation saves up to 40 pin counts (see table below) free for integrating more devices on a single chip.
Winbond I/O W83977EF W83627SF save
Interface pins D[7:0], SA[15:0], DRQ[3:0], DACK#[3:0], TC, IOR#, IOW#, IOCHRDY, IRQs LAD[3:0], LFRAME#, PCICLK, LDRQ#, SERIRQ, PME#
count 49 9 40
The transition from ISA to LPC is transparent in terms of software which means no BIOS or device driver update is needed except chip-specific configuration.
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY 3. FDC FUNCTIONAL DESCRIPTION
3.1 W83627SF FDC
The floppy disk controller of the W83627SF integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The digital data separator supports up to 2 M bits/sec data rate. The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital Data Separator, FIFO, and FDC Core.
3.1.1 AT interface The interface consists of the standard asynchronous signals: RD#, WR#, A0-A3, IRQ, DMA control, and a data bus. The address lines select between the configuration registers, the FIFO and control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal modes. The PS/2 register sets are a superset of the registers found in a PC/AT.
3.1.2 FIFO (Data) The FIFO is 16 bytes in size and has programmable threshold values.
All command parameter
information and disk data transfers go through the FIFO. Data transfers are governed by the RQM and DIO bits in the Main Status Register. The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware
compatibility. The default values can be changed through the CONFIGURE command. The advantage of the FIFO is that it allows the system a larger DMA latency without causing disk errors. The following tables give several examples of the delays with a FIFO. The data are based upon the following formula:
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
THRESHOLD # x (1/DATA/RATE) *8 - 1.5 S = DELAY FIFO THRESHOLD 1 Byte 2 Byte 8 Byte 15 Byte FIFO THRESHOLD 1 Byte 2 Byte 8 Byte 15 Byte MAXIMUM DELAY TO SERVICING AT 500K BPS Data Rate 1 x 16 S - 1.5 S = 14.5 S 2 x 16 S - 1.5 S = 30.5 S 8 x 16 S - 1.5 S = 6.5 S 15 x 16 S - 1.5 S = 238.5 S MAXIMUM DELAY TO SERVICING AT 1M BPS Data Rate 1 x 8 S - 1.5 S = 6.5 S 2 x 8 S - 1.5 S = 14.5 S 8 x 8 S - 1.5 S = 62.5 S 15 x 8 S - 1.5 S = 118.5 S
At the start of a command the FIFO is always disabled and command parameters must be sent based upon the RQM and DIO bit settings in the main status register. When the FDC enters the command execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred. An overrun and underrun will terminate the current command and the data transfer. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered. DMA transfers are enabled with the SPECIFY command and are initiated by the FDC by activating the DRQ pin during a data transfer command. The FIFO is enabled directly by asserting DACK# and addresses need not be valid. Note that if the DMA controller is programmed to function in verify mode a pseudo read is performed by the FDC based only on DACK#. This mode is only available when the FDC has been configured into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled the above operation is performed by using the new VERIFY command. No DMA operation is needed.@
3.1.3
Data Separator
The function of the data separator is to lock onto the incoming serial read data. When a lock is achieved the serial front end logic of the chip is provided with a clock which is synchronized to the read data. The synchronized clock, called the Data Window, is used to internally sample the serial data portion of the bit cell, and the alternate state samples the clock portion. Serial to parallel conversion logic separates the read data into clock and data bytes. The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking. The DDS circuit cycles once every 12 clock cycles ideally. Any data pulse input will be synchronized and then adjusted by immediate error adjustment. The control logic will generate RDD and RWD for every pulse input. During any cycle where no data pulse is present, the DDS cycles are based on speed. A digital integrator is used to keep track of the speed changes in the input data stream.
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
3.1.4
Write Precompensation
The write precompensation logic is used to minimize bit shifts in the RDDATA stream from the disk drive. Shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media and the floppy drive. The FDC monitors the bit stream that is being sent to the drive. The data patterns that require precompensation are well known. Depending upon the pattern, the bit is shifted either early or late relative to the surrounding bits.
3.1.5
Perpendicular Recording Mode
The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically. This scheme packs more data bits into the same area. FDCs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write perpendicular media. Some manufacturers offer drives that can read and write standard and perpendicular media in a perpendicular media drive. A single command puts the FDC into perpendicular mode. All other commands operate as they normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk.
3.1.6
FDC Core
The W83627SF FDC is capable of performing twenty commands. Each command is initiated by a multibyte transfer from the microprocessor. The result can also be a multi-byte transfer back to the microprocessor. Each command consists of three phases: command, execution, and result. Command The microprocessor issues all required information to the controller to perform a specific operation. Execution The controller performs the specified operation. Result After the operation is completed, status information and other housekeeping information is provided to the microprocessor.
3.1.7
FDC Commands
Command Symbol Descriptions: C: Cylinder number 0 - 256 D: Data Pattern DIR: Step Direction DIR = 0, step out Publication Release Date: Nov. 2000 Revision 0.60
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W83627SF
PRELIMINARY
DS0: DS1: DTL: EC: EOT: EFIFO: EIS: EOT: FIFOTHR: GAP: GPL: H: HDS: HLT: HUT: LOCK: MFM: MT: N: NCN: ND: OW: PCN: POLL: PRETRK: R: RCN: R/W: SC: SK: SRT: ST0: ST1: ST2: ST3: WG: DIR = 1, step in Disk Drive Select 0 Disk Drive Select 1 Data Length Enable Count End of Track Enable FIFO Enable Implied Seek End of track FIFO Threshold Gap length selection Gap Length Head number Head number select Head Load Time Head Unload Time Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset MFM or FM Mode Multitrack The number of data bytes written in a sector New Cylinder Number Non-DMA Mode Overwritten Present Cylinder Number Polling Disable Precompensation Start Track Number Record Relative Cylinder Number Read/Write Sector/per cylinder Skip deleted data address mark Step Rate Time Status Register 0 Status Register 1 Status Register 2 Status Register 3 Write gate alters timing of WE
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
(1) Read Data PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution D7 0 D6 0 D5 SK 0 D4 0 0 D3 0 0 D2 1 D1 1 D0 0 REMARKS Command codes Sector ID information prior to command execution
MT MFM
HDS DS1 DS0
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL -----------------------
Data transfer between the FDD and system Status information after command execution
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PRELIMINARY
(2) Read Deleted Data PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution D7 D6 D5 SK 0 D4 0 0 D3 1 0 D2 1 D1 0 D0 0 REMARKS Command codes
MT MFM 0 0
HDS DS1 DS0 Sector ID information prior to command execution
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL -----------------------
Data transfer between the FDD and system Status information after command execution
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PRELIMINARY
(3) Read A Track PHASE Command R/W W W W W W W W W W Execution D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 0 0 D2 0 D1 1 D0 0 REMARKS Command codes
HDS DS1 DS0 Sector ID information prior to command execution
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL -----------------------
Data transfer between the FDD and system; FDD reads contents of all cylinders from index hole to EOT R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution Status information after command execution
Result
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PRELIMINARY
(4) Read ID PHASE Command Execution R/W W W D7 D6 0 MFM 0 0 D5 0 0 D4 0 0 D3 1 0 D2 D1 D0 0 1 0 HDS DS1 DS0 REMARKS Command codes The first correct ID information on the cylinder is stored in Data Register Status information after command execution Disk status after the command has been completed
Result
R R R R R R R
-------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------
(5) Verify PHASE Command R/W W W W W W W W W D7 D6 D5 D4 D3 D2 D1 D0 MT MFM SK 1 0 1 1 0 EC 0 0 0 0 HDS DS1 DS0 ---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL/SC ------------------REMARKS Command codes Sector ID information prior to command execution
Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------
No data transfer takes place Status information after command execution Sector ID information after command execution
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PRELIMINARY
(6) Version PHASE Command Result (7) Write Data PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after Command execution D7 0 D6 0 D5 0 0 D4 0 0 D3 0 0 D2 1 D1 0 D0 1 REMARKS Command codes Sector ID information prior to Command execution R/W W R D7 0 1 D6 0 0 D5 0 0 D4 1 1 D3 0 0 D2 0 0 D1 0 0 D0 0 0 REMARKS Command code Enhanced controller
MT MFM
HDS DS1 DS0
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL -----------------------
Data transfer between the FDD and system Status information after Command execution
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PRELIMINARY
(8) Write Deleted Data PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution D7 0 D6 0 D5 0 0 D4 0 0 D3 1 0 D2 0 D1 0 D0 1 REMARKS Command codes Sector ID information prior to command execution
MT MFM
HDS DS1 DS0
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL -----------------------
Data transfer between the FDD and system Status information after command execution
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PRELIMINARY
(9) Format A Track PHASE Command R/W W W W W W W Execution for Each Sector Repeat: Result W W W W R R R R R R R D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 1 D1 0 D0 1 REMARKS Command codes Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters
HDS DS1 DS0
---------------------- N -------------------------------------------- SC ------------------------------------------- GPL ------------------------------------------ D --------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------- Undefined ---------------------------------- Undefined ---------------------------------- Undefined ---------------------------------- Undefined -------------------
Status information after command execution
(10) Recalibrate PHASE Command R/W W W Execution D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 1 0 D1 1 D0 1 REMARKS Command codes
DS1 DS0 Head retracted to Track 0 Interrupt
(11) Sense Interrupt Status PHASE Command Result R/W W R R D7 0 D6 0 D5 0 D4 0 D3 1 D2 0 D1 0 D0 0 REMARKS Command code Status information at the end of each seek operation
---------------- ST0 ---------------------------------------- PCN -------------------------
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PRELIMINARY
(12) Specify PHASE Command R/W W W W (13) Seek PHASE Command R/W W W W Execution R D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 1 0 D2 1 D1 1 D0 1 REMARKS Command codes D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 REMARKS
1 Command codes
| ---------SRT ----------- | --------- HUT ---------- | |------------ HLT ----------------------------------| ND
HDS DS1 DS0
-------------------- NCN ----------------------Head positioned over proper cylinder on diskette
(14) Configure PHASE Command R/W W W W W Execution (15) Relative Seek PHASE Command R/W W W W D7 1 0 D6 DIR 0 D5 0 0 D4 0 0 D3 1 0 D2 1 D1 1 D0 1 REMARKS Command codes D7 0 0 0 D6 0 0 D5 0 0 D4 1 0 D3 0 0 D2 0 0 D1 1 0 D0 1 0 REMARKS Configure information
EIS EFIFO POLL | ------ FIFOTHR ----|
| --------------------PRETRK ----------------------- | Internal registers written
HDS DS1 DS0
| -------------------- RCN ---------------------------- |
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PRELIMINARY
(16) Dumpreg PHASE Command Result R/W W R R R R R R R R R R D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 1 1 0 ----------------------- PCN-Drive 0------------------------------------------ PCN-Drive 1 ----------------------------------------- PCN-Drive 2------------------------------------------ PCN-Drive 3 --------------------------SRT ------------------ | --------- HUT ------------------ HLT -----------------------------------| ND ------------------------ SC/EOT ---------------------LOCK 0 D3 D2 D1 D0 GAP WG 0 EIS EFIFO POLL | ------ FIFOTHR ------------------------------PRETRK ------------------------REMARKS Registers placed in FIFO
(17) Perpendicular Mode PHASE Command R/W W W D7 0 OW D6 0 0 D5 0 D3 D4 1 D2 D3 0 D1 D2 D1 D0 0 1 0 D0 GAP WG REMARKS Command Code
(18) Lock PHASE Command Result R/W W R D7 D6 LOCK 0 0 0 D5 D4 D3 0 1 0 0 LOCK 0 D2 1 0 D1 0 0 D0 0 0 REMARKS Command Code
(19) Sense Drive Status PHASE Command Result R/W W W R D7 0 0 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 0 0 0 0 0 HDS DS1 DS0 ---------------- ST3 ------------------------REMARKS Command Code Status information about disk drive
(20) Invalid PHASE Command Result R/W W R D7 D6 D5 D4 D3 D2 D1 D0 ------------- Invalid Codes ------------------------------------ ST0 ---------------------REMARKS Invalid codes (no operationFDC goes to standby state) ST0 = 80H
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PRELIMINARY
3.2 Register Descriptions
ADDRESS OFFSET base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 base address + 5 base address + 7 TD REGISTER MS REGISTER DT (FIFO) REGISTER DI REGISTER READ SA REGISTER SB REGISTER DO REGISTER TD REGISTER DR REGISTER DT (FIFO) REGISTER CC REGISTER REGISTER WRITE
There are several status, data, and control registers in W83627SF. These registers are defined below:
3.2.1
Status Register A (SA Register) (Read base address + 0)
This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows:
7 6 5 4 3 2 1 0
DIR WP INDEX HEAD TRAK0 STEP DRV2 INIT PENDING
INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output. DRV2# (Bit 6): 0 A second drive has been installed 1 A second drive has not been installed STEP (Bit 5): This bit indicates the complement of STEP# output. TRAK0# (Bit 4): This bit indicates the value of TRAK0# input.
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PRELIMINARY
HEAD (Bit 3): This bit indicates the complement of HEAD# output. 0 side 0 1 side 1 INDEX# (Bit 2): This bit indicates the value of INDEX# output. WP# (Bit 1): 0 1 disk is write-protected disk is not write-protected
DIR (Bit 0) This bit indicates the direction of head movement. 0 1 outward direction inward direction
In PS/2 Model 30 mode, the bit definitions for this register are as follows: 7 6 5 4 3 2 1 0
DIR WP INDEX HEAD TRAK0 STEP F/F DRQ INIT PENDING INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output. DRQ (Bit 6): This bit indicates the value of DRQ output pin. STEP F/F (Bit 5): This bit indicates the complement of latched STEP# output. TRAK0 (Bit 4): This bit indicates the complement of TRAK0# input.
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PRELIMINARY
HEAD# (Bit 3): This bit indicates the value of HEAD# output. 0 1 side 1 side 0
INDEX (Bit 2): This bit indicates the complement of INDEX# output. WP (Bit 1): 0 1 disk is not write-protected disk is write-protected
DIR# (Bit 0) This bit indicates the direction of head movement. 0 1 inward direction outward direction
3.2.2
Status Register B (SB Register) (Read base address + 1)
This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows: 7 1 6 1 MOT EN A MOT EN B WE RDATA Toggle WDATA Toggle Drive SEL0 Drive SEL0 (Bit 5): This bit indicates the status of DO REGISTER bit 0 (drive select bit 0). WDATA Toggle (Bit 4): This bit changes state at every rising edge of the WD# output pin. RDATA Toggle (Bit 3): This bit changes state at every rising edge of the RDATA# output pin. WE (Bit 2): This bit indicates the complement of the WE# output pin. 5 4 3 2 1 0
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PRELIMINARY
MOT EN B (Bit 1) This bit indicates the complement of the MOB# output pin. MOT EN A (Bit 0) This bit indicates the complement of the MOA# output pin. In PS/2 Model 30 mode, the bit definitions for this register are as follows:
7 6 5 4 3 2 1 0
DSC DSD WE F/F RDATA F/F WD F/F DSA DSB DRV2
DRV2# (Bit 7): 0 1 A second drive has been installed A second drive has not been installed
DSB# (Bit 6): This bit indicates the status of DSB# output pin. DSA# (Bit 5): This bit indicates the status of DSA# output pin. WD F/F(Bit 4): This bit indicates the complement of the latched WD# output pin at every rising edge of the WD# output pin. RDATA F/F(Bit 3): This bit indicates the complement of the latched RDATA# output pin . WE F/F (Bit 2): This bit indicates the complement of latched WE# output pin. DSD# (Bit 1): 0 1 Drive D has been selected Drive D has not been selected
DSC# (Bit 0): 0 Drive C has been selected 1 Drive C has not been selected
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PRELIMINARY
3.2.3 Digital Output Register (DO Register) (Write base address + 2)
The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ enable, and FDC resetting. All the bits in this register are cleared by the MR pin. The bit definitions are as follows:
7 6 5 4 3 2 1-0 Drive Select: 00 select drive A 01 select drive B 10 select drive C 11 select drive D Floppy Disk Controller Reset Active low resets FDC DMA and INT Enable Active high enable DRQ/IRQ Motor Enable A. Motor A on when active high Motor Enable B. Motor B on when active high Motor Enable C. Motor C on when active high Motor Enable D. Motor D on when active high
3.2.4
Tape Drive Register (TD Register) (Read base address + 3)
This register is used to assign a particular drive number to the tape drive support mode of the data separator. This register also holds the media ID, drive type, and floppy boot drive information of the floppy disk drive. In normal floppy mode, this register includes only bit 0 and 1. The bit definitions are as follows:
7 X 6 X 5 X 4 X 3 X 2 X Tape sel 0 Tape sel 1 1 0
If three mode FDD function is enabled (EN3MODE = 1 in CR9), the bit definitions are as follows:
7 6 5 4 3 2 1 0
Tape Sel 0 Tape Sel 1 Floppy boot drive 0 Floppy boot drive 1 Drive type ID0 Drive type ID1 Media ID0 Media ID1
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PRELIMINARY
Media ID1 Media ID0 (Bit 7, 6): These two bits are read only. These two bits reflect the value of CR8 bit 3, 2. Drive type ID1 Drive type ID0 (Bit 5, 4): These two bits reflect two of the bits of CR7. Which two bits are reflected depends on the last drive selected in the DO REGISTER. Floppy Boot drive 1, 0 (Bit 3, 2): These two bits reflect the value of CR8 bit 1, 0. Tape Sel 1, Tape Sel 0 (Bit 1, 0): These two bits assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive and is reserved as the floppy disk boot drive. TAPE SEL 1 0 0 1 1 3.2.5 TAPE SEL 0 0 1 0 1 DRIVE SELECTED None 1 2 3
Main Status Register (MS Register) (Read base address + 4)
The Main Status Register is used to control the flow of data between the microprocessor and the controller. The bit definitions for this register are as follows:
7 6 5 4 3 2 1 0
FDD 0 Busy, (D0B = 1), FDD number 0 is in the SEEK mode. FDD 1 Busy, (D1B = 1), FDD number 1 is in the SEEK mode. FDD 2 Busy, (D2B = 1), FDD number 2 is in the SEEK mode. FDD 3 Busy, (D3B = 1), FDD number 3 is in the SEEK mode. FDC Busy, (CB). A read or write command is in the process when CB = HIGH. Non-DMA mode, the FDC is in the non-DMA mode, this bit is set only during the execution phase in non-DMA mode. Transition to LOW state indicates execution phase has ended. DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor. If DIO = LOW then transfer is from processor to Data Register. Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the proce
3.2.6
Data Rate Register (DR Register) (Write base address + 4)
The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of the FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and not by the DR REGISTER. The real data rate is determined by the most recent write to either of the DR REGISTER or CC REGISTER.
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PRELIMINARY
7 6 5 0 DRATE0 DRATE1 PRECOMP0 PRECOMP1 PRECOMP2 POWER DOWN S/W RESET 4 3 2 1 0
S/W RESET (Bit 7): This bit is the software reset bit. POWER-DOWN (Bit 6): 0 FDC in normal mode 1 FDC in power-down mode PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2): These three bits select the value of write precompensation. The following tables show the precompensation values for the combination of these bits. PRECOMP 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 PRECOMPENSATION DELAY 250K - 1 Mbps Default Delays 41.67 nS 83.34 nS 125.00 nS 166.67 nS 208.33 nS 250.00 nS 0.00 nS (disabled) 2 Mbps Tape drive Default Delays 20.8 nS 41.17 nS 62.5nS 83.3 nS 104.2 nS 125.00 nS 0.00 nS (disabled)
DATA RATE 250 KB/S 300 KB/S 500 KB/S 1 MB/S 2 MB/S
DEFAULT PRECOMPENSATION DELAYS 125 nS 125 nS 125 nS 41.67nS 20.8 nS
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DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC and reduced write current control. 00 500 KB/S (MFM), 250 KB/S (FM), RWC = 1 01 300 KB/S (MFM), 150 KB/S (FM), RWC = 0 10 250 KB/S (MFM), 125 KB/S (FM), RWC = 0 11 1 MB/S (MFM), Illegal (FM), RWC = 1 The 2 MB/S data rate for Tape drive is only supported by setting 01 to DRATE1 and DRATE0 bits, as well as setting 10 to DRT1 and DRT0 bits which are two of the Configure Register CRF4 or CRF5 bits in logic device 0. Please refer to the function description of CRF4 or CRF5 and data rate table for individual data rates setting. 3.2.7 FIFO Register (R/W base address + 5)
The Data Register consists of four status registers in a stack with only one register presented to the data bus at a time. This register stores data, commands, and parameters and provides diskette-drive status information. Data bytes are passed through the data register to program or obtain results after a command. In the W83627SF, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command. Status Register 0 (ST0)
7-6 5 4 3 2 1-0
US1, US0 Drive Select: 00 Drive A selected 01 Drive B selected 10 Drive C selected 11 Drive D selected HD Head address: 1 Head selected 0 Head selected NR Not Ready: 1 Drive is not ready 0 Drive is ready EC Equipment Check: 1 When a fault signal is received from the FDD or the track 0 signal fails to occur after 77 step pulses 0 No error SE Seek end: 1 seek end 0 seek error IC Interrupt Code: 00 Normal termination of command 01 Abnormal termination of command 10 Invalid command issue 11 Abnormal termination because the ready signal from FDD changed state during command execution
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PRELIMINARY
Status Register 1 (ST1)
7 6 5 4 3 2 1 0
Missing Address Mark. 1 When the FDC cannot detect the data address mark or the data address mark has been deleted.
NW (Not Writable). 1 If a write Protect signal is detected from the diskette drive during execution of write data. ND (No DATA). 1 If specified sector cannot be found during execution of a read, write or verifly data. Not used. This bit is always 0. OR (Over Rum). 1 If the FDC is not serviced by the host system within a certain time interval during data transfer. DE (data Error).1 When the FDC detects a CRC error in either the ID field or the data field. Not used. This bit is always 0. EN (End of track). 1 When the FDC tries to access a sector beyond the final sector of a cylinder.
Status Register 2 (ST2)
7 6 5 4 3 2 1 0
MD (Missing Address Mark in Data Field). 1 If the FDC cannot find a data address mark (or the address mark has been deleted) when reading data from the media 0 No error BC (Bad Cylinder) 1 Bad Cylinder 0 No error SN (Scan Not satisfied) 1 During execution of the Scan command 0 No error SH (Scan Equal Hit) 1 During execution of the Scan command, if the equal condition is satisfied 0 No error WC (Wrong Cylinder) 1 Indicates wrong Cylinder DD (Data error in the Data field) 1 If the FDC detects a CRC error in the data field 0 No error CM (Control Mark) 1 During execution of the read data or scan command 0 No error Not used. This bit is always 0
Status Register 3 (ST3)
7 6 5 4 3 2 1 0
US0 Unit Select 0 US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 RY Ready WP Write Protected FT Fault
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PRELIMINARY
3.2.8 Digital Input Register (DI Register) (Read base address + 7)
The Digital Input Register is an 8-bit read-only register used for diagnostic purposes. In a PC/XT or AT only Bit 7 is checked by the BIOS. When the register is read, Bit 7 shows the complement of DSKCHG#, while other bits of the data bus remain in tri-state. Bit definitions are as follows:
7 6 5 4 3 2 1 0
x
x
xx
xxx for hard disk controller x Reservedreadthethis register, these bits are in tri-state During a of
DSKCHG
In the PS/2 mode, the bit definitions are as follows:
7 6 1 5 1 4 1 3 1 HIGH DENS DRATE0 DRATE1 2 1 0
DSKCHG
DSKCHG (Bit 7): This bit indicates the complement of the DSKCHG# input. Bit 6-3: These bits are always a logic 1 during a read. DRATE1 DRATE0 (Bit 2, 1): These two bits select the data rate of the FDC. Refer to the DR register bits 1 and 0 for the settings corresponding to the indivi dual data rates. HIGH DENS# (Bit 0): 0 500 KB/S or 1 MB/S data rate (high density FDD) 1 250 KB/S or 300 KB/S data rate In the PS/2 Model 30 mode, the bit definitions are as follows:
7 6 0 5 0 4 0 DRATE0 DRATE1 NOPREC DMAEN 3 2 1 0
DSKCHG
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DSKCHG (Bit 7): This bit indicates the status of DSKCHG# input. Bit 6-4: These bits are always a logic 1 during a read. DMAEN (Bit 3): This bit indicates the value of DO REGISTER bit 3. NOPREC (Bit 2): This bit indicates the value of CC REGISTER NOPREC bit. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. 3.2.9 Configuration Control Register (CC Register) (Write base address + 7)
This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as follows:
7 6 5 4 3 2 1 0
x
x
x
x
x
x
DRATE0 DRATE1
X: Reserved Bit 7-2: Reserved. These bits should be set to 0. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. In the PS/2 Model 30 mode, the bit definitions are as follows:
7 X 6 X 5 X 4 X 3 X DRATE0 DRATE1 NOPREC 2 1 0
X: Reserved Bit 7-3: Reserved. These bits should be set to 0. NOPREC (Bit 2): This bit indicates no precompensation. It has no function and can be set by software. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. Publication Release Date: Nov. 2000 Revision 0.60
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W83627SF
PRELIMINARY 4. UART PORT
4.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B)
The UARTs are used to convert parallel data into serial format on the transmit side and convert serial data to parallel format on the receiver side. The serial format, in order of transmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five-bit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use this 16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the UARTs also include complete modem control capability and a processor interrupt system that may be software trailed to the computing time required to handle the communication link. The UARTs have a FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16-byte FIFOs for both receive and transmit mode.
4.2 Register Address
4.2.1 UART Control Register (UCR) (Read/Write) The UART Control Register controls and defines the protocol for asynchronous data communications, including data length, stop bit, parity, and baud rate selection.
7 6 5 4 3 2 1 0
Data length select bit 0 (DLS0) Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB)
Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary format) from the divisor latches of the baudrate generator during a read or write operation. When this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the Interrupt Control Register can be accessed. Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is affected by this bit; the transmitter is not affected. Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1, (1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check. (2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check.
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TABLE 4-1 UART Register Bit Map Bit Number
Register Address Base +0 BDLAB = 0 Receiver Buffer Register (Read Only) RBR 0 RX Data Bit 0 1 RX Data Bit 1 2 RX Data Bit 2 3 RX Data Bit 3 4 RX Data Bit 4 5 RX Data Bit 5 6 RX Data Bit 6 7 RX Data Bit 7
+0 Transmitter BDLAB = 0 Buffer Register (Write Only) +1 Interrupt Control Register BDLAB = 0
TBR
TX Data Bit 0 RBR Data Ready Interrupt Enable (ERDRI) "0" if Interrupt Pending FIFO Enable
TX Data Bit 1 TBR Empty Interrupt Enable (ETBREI) Interrupt Status Bit (0) RCVR FIFO Reset Data Length Select Bit 1 (DLS1) Request to Send (RTS) Overrun Error (OER) DSR Toggling (TDSR) Bit 1 Bit 1
TX Data Bit 2 USR Interrupt Enable (EUSRI) Interrupt Status Bit (1) XMIT FIFO Reset Multiple Stop Bits Enable (MSBE) Loopback RI Input Parity Bit Error (PBER) RI Falling Edge (FERI) Bit 2 Bit 2
TX Data Bit 3 HSR Interrupt Enable (EHSRI) Interrupt Status Bit (2)** DMA Mode Select Parity Bit Enable (PBE) IRQ Enable
TX Data Bit 4 0
TX Data Bit 5 0
TX Data Bit 6 0
TX Data Bit 7 0
ICR
+2
Interrupt Status Register (Read Only) UART FIFO Control Register (Write Only) UART Control Register
ISR
0
0
FIFOs Enabled **
FIFOs Enabled **
+2
UFR
Reserved
Reversed
RX RX Interrupt Interrupt Active Level Active Level (LSB) (MSB) Set Silence Enable (SSE) 0 Baudrate Divisor Latch Access Bit (BDLAB) 0
+3
UCR
Data Length Select Bit 0 (DLS0) Data Terminal Ready (DTR) RBR Data Ready (RDR) CTS Toggling (TCTS) Bit 0 Bit 0
Even Parity Enable (EPE) Internal Loopback Enable Silent Byte Detected (SBD) Clear to Send (CTS) Bit 4 Bit 4
Parity Bit Fixed Enable PBFE) 0
+4
Handshake Control Register UART Status Register
HCR
+5
USR
No Stop Bit Error (NSER) DCD Toggling (TDCD) Bit 3 Bit 3
TBR Empty (TBRE) Data Set Ready (DSR) Bit 5 Bit 5
TSR Empty (TSRE) Ring Indicator (RI) Bit 6 Bit 6
RX FIFO Error Indication (RFEI) ** Data Carrier Detect (DCD) Bit 7 Bit 7
+6
Handshake Status Register User Defined Register Baudrate Divisor Latch Low Baudrate Divisor Latch High
HSR
+7 +0 BDLAB = 1 +1 BDLAB = 1
UDR BLL
BHL
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received. **: These bits are always 0 in 16450 Mode.
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W83627SF
PRELIMINARY
Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit 3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. When the bit is reset, an odd number of logic 1's are sent or checked. Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT will be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same position as the transmitter will be detected. Bit 2: MSBE. This bit defines the n umber of stop bits in each serial character that is transmitted or received. (1) If MSBE is set to a logical 0, one stop bit is sent and checked. (2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and checked. (3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and checked. Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in each serial character.
TABLE 4-2 WORD LENGTH DEFINITION
DLS1 0 0 1 1
DLS0 0 1 0 1
DATA LENGTH 5 bits 6 bits 7 bits 8 bits
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
4.2.2 UART Status Register (USR) (Read/Write) This 8-bit register provides information about the status of the data transfer during communication.
7 6 5 4 3 2 1 0
RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI)
Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic 1 when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO. In 16550 mode, this bit is cleared by reading from the USR if there are no remaining errors left in the FIFO. Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In 16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other thanthese two cases, this bit will be reset to a logical 0. Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be set to a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU to write the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO is empty. It will be reset to a logical 0 when the CPU writes data into TBR or FIFO. Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full word time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next received data before they were read by the CPU. In 16550 mode, it indicates the same condition instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0. Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
4.2.3 Handshake Control Register (HCR) (Read/Write) This register controls the pins of the UART used for handshaking peripherals such as modem, and controls the diagnostic mode of the UART.
7 0 6 0 5 0 Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable Internal loopback enable 4 3 2 1 0
Bit 4: When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback, as follows: (1) SOUT is forced to logical 1, and SIN is isolated from the communication link instead of the TSR. (2) Modem output pins are set to their inactive state. (3) Modem input pins are isolated from the communication link and connect internally as DTR (bit 0 of HCR) DSR, RTS ( bit 1 of HCR) CTS , Loopback RI input ( bit 2 of HCR) RI and IRQ enable ( bit 3 of HCR) DCD . Aside from the above connections, the UART operates normally. This method allows the CPU to test the UART in a convenient way. Bit 3: The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode this bit is internally connected to the modem control input DCD . Bit 2: This bit is used only in the diagnostic mode. connected to the modem control input RI . Bit 1: This bit controls the RTS output. The value of this bit is inverted and output to RTS . Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR . In the diagnostic mode this bit is internally
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
4.2.4 Handshake Status Register (HSR) (Read/Write) This register reflects the current state of four input pins for handshake peripherals such as a modem and records changes on these pins.
7 6 5 4 3 2 1 0
CTS toggling (TCTS) DSR toggling (TDSR) RI falling edge (FERI) DCD toggling (TDCD) Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD)
Bit 7: This bit is the opposite of the DCD input. This bit is equivalent to bit 3 of HCR in loopback mode. Bit 6: This bit is the opposite of the RI input. This bit is equivalent to bit 2 of HCR in loopback mode. Bit 5: This bit is the opposite of the DSR input. This bit is equivalent to bit 0 of HCR in loopback mode. Bit 4: This bit is the opposite of the CTS input. This bit is equivalent to bit 1 of HCR in loopback mode. Bit 3: TDCD. This bit indicates that the DCD pin has changed state after HSR was read by the CPU.
Bit 2: FERI. This bit indicates that the RI pin has changed from low to high state after HSR was read by the CPU. Bit 1: TDSR. This bit indicates that the DSR pin has changed state after HSR was read by the CPU. Bit 0: TCTS. This bit indicates that the CTS pin has changed state after HSR was read.
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Publication Release Date: Nov. 2000 Revision 0.60
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PRELIMINARY
4.2.5 UART FIFO Control Register (UFR) (Write only) This register is used to control the FIFO functions of the UART.
7 6 5 4 3 2 1 0
FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB)
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO. TABLE 4-3 FIFO TRIGGER LEVEL BIT 7 0 0 1 1 Bit 4, 5: Reserved Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if UFR bit 0 = 1. Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to a logical 0 by itself after being set to a logical 1. Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to a logical 0 by itself after being set to a logical 1. Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before other bits of UFR are programmed. BIT 6 0 1 0 1 RX FIFO INTERRUPT ACTIVE LEVEL (BYTES) 01 04 08 14
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
4.2.6 Interrupt Status Register (ISR) (Read only) This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3 bits.
7 6 5 0 4 0 0 if interrupt pending Interrupt Status bit 0 Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled FIFOs enabled 3 2 1 0
Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1. Bit 5, 4: These two bits are always logic 0. Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time-out interrupt is pending. Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below. Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred, this bit will be set to a logical 0. TABLE 4-4 INTERRUPT CONTROL FUNCTION ISR
Bit 3 0 0 0 Bit 2 0 1 1 Bit 1 0 1 0 Bit 0 1 0 0 Interrupt priority First Second Interrupt Type UART Receive Status RBR Data Ready
INTERRUPT SET AND FUNCTION
Interrupt Source No Interrupt pending 1. OER = 1 2. PBER =1 3. NSER = 1 4. SBD = 1 1. RBR data ready 2. FIFO interrupt active level reached Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. TBR empty Read USR 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR Clear Interrupt -
1
1
0
0
Second
FIFO Data Timeout
0
0
1
0
Third
TBR Empty
1. Write data into TBR 2. Read ISR (if priority is third) Read HSR
0
0
0
0
Fourth
Handshake status
1. TCTS = 1 2. TDSR = 1 3. FERI = 1 4. TDCD = 1
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
4.2.7 Interrupt Control Register (ICR) (Read/Write) This 8 -bit register allows the five types of controller interrupts to activate the interrupt output signal separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this register to a logical 1.
7 0 6 0 5 0 4 0 RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI) 3 2 1 0
Bit 7-4: These four bits are always logic 0. Bit 3: EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt. Bit 2: EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt. Bit 1: ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt. Bit 0: ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt.
4.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to
16
generate a 1.8461 MHz frequency and divides it by a divisor from 1 to 2 -1. The output frequency of the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter and receiver. The table in the next page illustrates the use of the baud generator with a frequency of 1.8461 MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable baud generator directly uses 24 MHz and the same divisor as the normal speed divisor. In high-speed mode, the data transmission rate can be as high as 1.5M bps.
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
4.2.9 User-defined Register (UDR) (Read/Write) This is a temporary register that can be accessed and defined by the user. TABLE 4-5 BAUD RATE TABLE BAUD RATE FROM DIFFERENT PRE-DIVIDER Pre-Div: 13 1.8461M Hz 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 Pre-Div:1.625 14.769M Hz 400 600 880 1076 1200 2400 4800 9600 14400 16000 19200 28800 38400 57600 76800 153600 307200 460800 921600 Pre-Div: 1.0 24M Hz 650 975 1430 1478.5 1950 3900 7800 15600 23400 26000 31200 46800 62400 93600 124800 249600 499200 748800 1497600 Decimal divisor used to generate 16X clock 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 1 Error Percentage between desired and actual ** ** 0.18% 0.099% ** ** ** ** ** 0.53% ** ** ** ** ** ** ** ** **
** The percentage error for all baud rates, except where indicated otherwise, is 0.16%. Note. Pre-Divisor is determined by CRF0 of UART A and B.
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY 5. CIR RECEIVER PORT
5.1 CIR Registers
5.1.1 Bank0.Reg0 - Receiver Buffer Registers (RBR) (Read) Receiver Buffer Register is read only. When the CIR pulse train has been detected and passed by the internal signal filter, the data samped and shifted into shifter register will write into Receiver Buffer Register. In the CIR, this port is only supports PIO mode and the address port is defined in the PnP. 5.1.2 Bank0.Reg1 - Interrupt Control Register (ICR) Power on default <7:0> = 00000000 binary Bit 7 6-3 2 1 0 Name EN_GLBI Reserved EN_TMR_I En_LSR_I EN_RX_I Read/Write Read/Write Read/Write Read/Write Read/Write Description Enable Global Interrupt. Write 1, enable interrupt. Write 0, disable global interrupt. Reserved Enable Timer Interrupt. Enable Line-Status-Register interrupt. Receiver Thershold-Level Interrupt Enable.
5.1.3 Bank0.Reg2 - Interrupt Status Register (ISR) Power on default <7:0> = 00000000 binary Bit 7-3 2 TMR_I Name Reserved Read Only Read/Write Reserved Timer Interrupt. Set to 1 when timer count to 0. This bit will be affected by (1) the timer registers are defined in Bank4.Reg0 and Bank1.Reg0~1, (2) EN_TMR(Enable Timer, in Bank0.Reg3.Bit2) should be set to 1, (3) ENTMR_I (Enable Timer Interrupt, in Bank0.Reg1.Bit2) should be set to 1. Line-Status-Register interrupt. Set to 1 when overrun, or parity bit, or stop bit, or silent byte detected error in the Line Status Register (LSR) sets to 1. Clear to 0 when LSR is read. Receiver Thershold-Level Interrupt. Set to 1 when (1) the Receiver Buffer Register (RBR) is equal or larger than the threshold level, (2) RBR occurs time-out if the receiver buffer register has valid data and below the threshold level. Clear to 0 when RBR is less than threshold level from reading RBR. Description
1
LSR_I
Read Only
0
RXTH_I
Read Only
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Publication Release Date: Nov. 2000 Revision 0.60
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PRELIMINARY
5.1.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) Power on default <7:0> = 00000000 binary Bit 7-6 Name BNK_SEL<1:0> Read/Write Read/Write Description Bank Select Register. These two bits are shared same address so that Bank Select Register (BSR) can be programmed to desired Bank in any Bank. BNK_SEL<1:0> = 00 Select Bank 0. BNK_SEL<1:0> = 01 Select Bank 1. BNK_SEL<1:0> = Reserved. BNK_SEL<1:0> = Reserved. Receiver FIFO Threshold Level. It is to determine the RXTH_I to become 1 when the Receiver FIFO Threshold Level is equal or larger than the defined value shown as follow. RXFTL<1:0> = 00 -- 1 byte RXFTL<1:0> = 01 -- 4 bytes RXFTL<1:0> = 10 -- 8 bytes RXFTL<1:0> = 11 -- 14 bytes Timer Test. Write to 1, then reading the TMRL/TMRH will return the programmed values of TMRL/TMRH, that is, does not return down count counter value. This bit is for test timer register. Enable timer. Write to 1, enable the timer Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to a logical 0 by itself after being set to a logical 1. Timer input clock. Winbond test register
5-4
RXFTL1/0
Read/Write
3
TMR_TST
Read/Write
2 1
EN_TMR RXF_RST
Read/Write Read/Write
0
TMR_CLK
Read/Write
5.1.5 Bank0.Reg4 - CIR Control Register (CTR) Power on default <7:0> = 0010,1001 binary Bit 7-5 Name RX_FR<2:0> Read/Write Read/Write Description Receiver Frequency Range 2~0. These bits select the input frequency of the receiver ranges. For the input signal, that is through a band pass filter, i.e., the frequency of the input signal is located at this defined range then the signal will be received. Receiver Frequency Select 4~0. Select the receiver operation frequency.
4-0
RX_FSL<4:0>
Read/Write
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PRELIMINARY
Table: Low Frequency range select of receiver.
RX_FR2~0 (Low Frequency) 001 RX_FSL4~0 00010 00011 00100 00101 00110 00111 01000 01001 01011 01100 01101 01111 10000 10010 10011 10101 10111 11010 11011 11101 Min. 26.1 28.2 29.4 30.0 31.4 32.1 32.8 33.6* 34.4 36.2 37.2 38.2 40.3 41.5 42.8 44.1 45.5 48.7 50.4 54.3 Max. 29.6 32.0 33.3 34.0 35.6 36.4 37.2 38.1* 39.0 41.0 42.1 43.2 45.7 47.1 48.5 50.0 51.6 55.2 57.1 61.5 Min. 24.7 26.7 27.8 28.4 29.6 30.3 31.0 31.7 32.5 34.2 35.1 36.0 38.1 39.2 40.4 41.7 43.0 46.0 47.6 51.3 010 Max. 31.7 34.3 35.7 36.5 38.1 39.0 39.8 40.8 41.8 44.0 45.1 46.3 49.0 50.4 51.9 53.6 55.3 59.1 61.2 65.9 Min. 23.4 25.3 26.3 26.9 28.1 28.7 29.4 30.1 30.8 32.4 33.2 34.1 36.1 37.2 38.3 39.5 40.7 43.6 45.1 48.6 011 Max. 34.2 36.9 38.4 39.3 41.0 42.0 42.9 44.0 45.0 47.3 48.6 49.9 52.7 54.3 56.0 57.7 59.6 63.7 65.9 71.0
Note that the other non-defined values are reserved.
5.1.6 Bank0.Reg5 - UART Line Status Register (USR) Power on default <7:0> = 0000,0000 binary Bit 7-3 2 1 0 Name Reserved RX_TO OV_ERR RDR Read/Write Read/Write Read/Write Read/Write Description Set to 1 when receiver FIFO or frame status FIFO occurs time-out. Read this bit will be cleared. Received FIFO overrun. Read to clear. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.
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Publication Release Date: Nov. 2000 Revision 0.60
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PRELIMINARY
5.1.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG) Power on default <7:0> = 0000,0000 binary Bit 7-6 Name SMPSEL<1:0> Read/Write Read/Write Description Sampling Mode Select. Select internal decoder methodology from the internal filter. Selected decoder mode will determine the receive data format. The sampling mode is shown as bellow: SMPSEL<1:0> = 00 T-Period Sample Mode. SMPSEL<1:0> = 01 Over-Sampling Mode. SMPSEL<1:0> = 10 Over-Sampling with re-sync. SMPSEL<1:0> = 11 FIFO Test Mode. The T-period code format is defined as follows. (Number of bits) - 1
B7 B6 B5 B4 B3 B2 B1 B0
Bit value The Bit value is set to 0, then the high pulse will be received. The Bit value is set to 1, then no energy will be received. The opposite results will be generated when the bit RXINV (Bank0.Reg6.Bit0) is set to 1. 5-4 LP_SL<1:0> Read/Write Low pass filter source selcetion. LP_SL<1:0> = 00 Select raw IRRX signal. LP_SL<1:0> = 01 Select R.B.P. signal LP_SL<1:0> = 10 Select D.B.P. signal. LP_SL<1:0> = 11 Reserved. Receiver Demodulation Source Selection. RXDMSL<1:0> = 00 select B.P. and L.P. filter. RXDMSL<1:0> = 01 select B.P. but not L.P. RXDMSL<1:0> = 10 Reserved. RXDMSL<1:0> = 11 do not pass demodulation. Baud Rate Pre-divisor. Set to 1, the baud rate generator input clock is set to 1.8432M Hz which is set to pre-divisor into 13. When set to 0, the pre-divisor is set to 1, that is, the input clock of baud rate generator is set to 24M Hz. Receiving Signal Invert. Write to 1, Invert the receiving signal.
3-2
RXDMSL<1:0>
Read/Write
1
PRE_DIV
Read/Write
0
RXINV
Read/Write
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
5.1.8 Bank0.Reg7 - User Defined Register (UDR/AUDR) Power on default <7:0> = 0000,0000 binary Bit 7 Name RXACT Read/Write Read/Write Description Receive Active. Set to 1 whenever a pulse or pulse-train is detected by the receiver. If a 1 is written into the bit position, the bit is cleared and the receiver is de-actived. When this bit is set, the receiver samples the IR input continuously at the programmed baud rate and transfers the data to the receiver FIFO. Set to 1 whenever a pulse or pulse-train (modulated pulse) is detected by the receiver. Can be used by the sofware to detect idle condition Cleared Upon Read. FIFO Level Value. Indicate that how many bytes are there in the current received FIFO. Can read these bits then get the FIFO level value and successively read RBR by the prior value.
6
RX_PD
Read Only
5 4-0
Reserved FOLVAL
Read Only
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Publication Release Date: Nov. 2000 Revision 0.60
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PRELIMINARY
5.1.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) The two registers of BLL and BHL are baud rate divisor latch in the legacy UART/SIR/ASK-IR mode. Read/Write these registers, if set in Advanced UART mode, will occur backward operation, that is, will go to legacy UART mode and clear some register values shown table as follows. TABLE :BAUD RATE TABLE BAUD RATE USING 24 MHZ TO GENERATE 1.8461 MHZ Desired Baud Rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 1.5M 1 Decimal divisor used to generate 16X clock 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 1
Note 1
Percent error difference between desired and actual ** ** 0.18% 0.099% ** ** ** ** ** 0.53% ** ** ** ** ** ** ** ** ** 0%
Note 1: Only use in high speed mode, when Bank0.Reg6.Bit7 is set. ** The percentage error for all baud rates, except where indicated otherwise, is 0.16%
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
5.1.10 Bank1.Reg2 - Version ID Regiister I (VID) Power on default <7:0> = 0001,0000 binary Bit 7-0 VID Name Read/Write Read Only Description Version ID, default is set to 0x10.
5.1.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) This register is defined same as in Bank0.Reg3.
5.1.12 Bank1.Reg4 - Timer Low Byte Register (TMRL) Power on default <7:0> = 0000,0000 binary Bit 7-0 TMRL Name Read/Write Read/Write Description Timer Low Byte Register. This is a 12-bit timer (another 4bit is defined in Bank1.Reg5) which resolution is 1 ms, that is, the programmed maximum time is 2 -1 ms. The timer is a down-counter. The timer start down count when the bit EN_TMR (Enable Timer) of Bank0.Reg2. is set to 1. When the timer down count to zero and EN_TMR=1, the TMR_I is set to 1. When the counter down count to zero, a new initial value will be re-loaded into timer counter.
12
5.1.13 Bank1.Reg5 - Timer High Byte Register (TMRH) Power on default <7:0> = 0000,0000 binary Bit 7-4 3-0 TMRH Name Reserved Read/Write Read/Write Reserved. Timer High Byte Register. See Bank1.Reg4. Description
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY 6. PARALLEL PORT
6.1 Printer Interface Logic
The parallel port of the W83627SF makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. The W83627SF supports an IBM XT/AT compatible parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode (EXT2FDD) on the parallel port. Refer to the configuration registers for more information on disabling, power-down, and on selecting the mode of operation. Table 6-1 shows the pin definitions for different modes of the parallel port.
TABLE 6-1-1 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS HOST CONNECTOR 1 2-9 10 11 12 13 14 15 16 17 Notes: n : Active Low 1. Compatible Mode 2. High Speed Mode 3. For more information, refer to the IEEE 1284 standard. PIN NUMBER OF W83627SF 36 31-26, 24-23 22 21 19 18 35 34 33 32 PIN ATTRIBUTE O I/O I I I I O I O O SPP nSTB PD<0:7> nACK BUSY PE SLCT nAFD nERR nINIT nSLIN EPP nWrite PD<0:7> Intr nWait PE Select nDStrb nError nInit nAStrb ECP nSTB, HostClk2 PD<0:7> nACK, PeriphClk2 BUSY, PeriphAck2 PEerror, nAckReverse2 SLCT, Xflag2 nAFD, HostAck2 nFault1, nPeriphRequest2 nINIT1, nReverseRqst2 nSLIN1 , ECPMode2
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PRELIMINARY
TABLE 6-1-2 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS HOST CONNECTOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PIN NUMBER OF W83627SF 36 31 30 29 28 27 26 24 23 22 21 19 18 35 34 33 32 PIN ATTRIBUTE O I/O I/O I/O I/O I/O I/O I/O I/O I I I I O I O O SPP nSTB PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 nACK BUSY PE SLCT nAFD nERR nINIT nSLIN PIN ATTRIBUTE --I I I I I --OD OD OD OD OD OD OD OD OD OD EXT2FDD --INDEX2# TRAK02# WP2# RDATA2# DSKCHG2# --MOA2# DSA2# DSB2# MOB2# WD2# WE2# RWC2# HEAD2# DIR2# STEP2# PIN ATTRIBUTE --I I I I I ------OD OD OD OD OD OD OD OD EXTFDD --INDEX2# TRAK02# WP2# RDATA2# DSKCHG2# ------DSB2# MOB2# WD2# WE2# RWC2# HEAD2# DIR2# STEP2#
6.2 Enhanced Parallel Port (EPP)
TABLE 6-2 PRINTER MODE AND EPP REGISTER ADDRESS A2 0 0 0 0 0 1 1 1 1
Notes: 1. These registers are available in all modes. 2. These registers are available only in EPP mode.
A1 0 0 1 1 1 0 0 1 1
A0 0 1 0 0 1 0 1 0 1
REGISTER Data port (R/W) Printer status buffer (Read) Printer control latch (Write) Printer control swapper (Read) EPP address port (R/W) EPP data port 0 (R/W) EPP data port 1 (R/W) EPP data port 2 (R/W) EPP data port 2 (R/W)
NOTE 1 1 1 1 2 2 2 2 2
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Publication Release Date: Nov. 2000 Revision 0.60
W83627SF
PRELIMINARY
6.2.1 Data Swapper The system microprocessor can read the contents of the printer's data latch by reading the data swapper.
6.2.2 Printer Status Buffer The system microprocessor can read the printer status by reading the address of the printer status buffer. The bit definitions are as follows:
7 6 5 4 3 2 1 1 1 TMOUT ERROR SLCT PE ACK BUSY 0
Bit 7: This signal is active during data entry, when the printer is off-line during printing, when the print head is changing position, or during an error state. When this signal is active, the printer is busy and cannot accept data. Bit 6: This bit represents the current state of the printer's ACK# signal. A 0 means the printer has received a character and is ready to accept another. Normally, this signal will be active for approximately 5 microseconds before BUSY# stops. Bit 5: Logical 1 means the printer has detected the end of paper. Bit 4: Logical 1 means the printer is selected. Bit 3: Logical 0 means the printer has encountered an error condition. Bit 1, 2: These two bits are not implemented and are logic one during a read of the status register. Bit 0: This bit is valid in EPP mode only. It indicates that a 10 S time-out has occurred on the EPP bus. A logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error has been detected. Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0 has no effect.
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6.2.3 Printer Control Latch and Printer Control Swapper The system microprocessor can read the contents of the printer control latch by reading the printer control swapper. Bit definitions are as follows:
7 1 6 1 STROBE AUTO FD INIT SLCT IN IRQ ENABLE DIR 5 4 3 2 1 0
Bit 7, 6: These two bits are a logic one during a read. They can be written. Bit 5: Direction control bit When this bit is a logic 1, the parallel port is in input mode (read); when it is a logic 0, the parallel port is in output mode (write). This bit can be read and written. In SPP mode, this bit is invalid and fixed at zero. Bit 4: A 1 in this position allows an interrupt to occur when ACK# changes from low to high. Bit 3: A 1 in this bit position selects the printer. Bit 2: A 0 starts the printer (50 microsecond pulse, minimum). Bit 1: A 1 causes the printer to line-feed after a line is printed. Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must b e present for a minimum of 0.5 microseconds before and after the strobe pulse.
6.2.4 EPP Address Port The address port is available only in EPP mode. Bit definitions are as follows:
7 6 5 4 3 2 1 0
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
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The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP address write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the EPP write cycle. PD0-PD7 ports are read during a read operation. The leading edge of IOR# causes an EPP address read cycle to be performed and the data to be output to the host CPU.
6.2.5 EPP Data Port 0-3 These four registers are available only in EPP mode. Bit definitions of each data port are as follows:
7 6 5 4 3 2 1 0
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (non-inverting) and output to the ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP data write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the EPP write cycle. During a read operation, ports PD0-PD7 are read, and the leading edge of IOR# causes an EPP read cycle to be performed and the data to be output to the host CPU. 6.2.6 Bit Map of Parallel Port and EPP Registers
REGISTER Data Port (R/W) Status Buffer (Read) Control Swapper (Read) Control Latch (Write) EPP Address Port R/W) EPP Data Port 0 (R/W) EPP Data Port 1 (R/W) EPP Data Port 2 (R/W) EPP Data Port 3 (R/W)
7 PD7 BUSY# 1 1 PD7 PD7 PD7 PD7 PD7
6 PD6 ACK# 1 1 PD6 PD6 PD6 PD6 PD6
5 PD5 PE 1 DIR PD5 PD5 PD5 PD5 PD5
4 PD4 SLCT IRQEN IRQ PD4 PD4 PD4 PD4 PD4
3 PD3
ERROF#
2 PD2 1 INIT# INIT# PD2 PD2 PD2 PD2 PD2
1 PD1 1 AUTOFD# AUTOFD# PD1 PD1 PD1 PD1 PD1
0 PD0 TMOUT STROBE# STROBE# PD0 PD0 PD0 PD0 PD0
SLIN SLIN PD3 PD3 PD3 PD3 PD3
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6.2.7 EPP Pin Descriptions TYPE O I/O I I I I O I O O EPP DESCRIPTION Denotes an address or data read or write operation. Bi-directional EPP address and data bus. Used by peripheral device to interrupt the host. Inactive to acknowledge that data transfer is completed. Active to indicate that the device is ready for the next transfer. Paper end; same as SPP mode. Printer selected status; same as SPP mode. This signal is active low. It denotes a data read or write operation. Error; same as SPP mode. This signal is active low. When it is active, the EPP device is reset to its initial operating mode. This signal is active low. It denotes an address read or write operation. EPP NAME nWrite PD<0:7> Intr nWait PE Select nDStrb nError nInits nAStrb
6.2.8 EPP Operation When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available. The PDx bus is in the standard or b i-directional mode when no EPP read, write, or address cycle is currently being executed. In this condition all output signals are set by the SPP Control Port and the direction is controlled by DIR of the Control Port. A watchdog timer is required to prevent system lockup. The timer indicates that more than 10 S have elapsed from the start of the EPP cycle to the time WAIT# is deasserted. The current EPP cycle is aborted when a time-out occurs. The time-out condition is indicated in Status bit 0. 6.2.8.1 EPP Operation The EPP operates on a two-phase cycle. First, the host selects the register within the device for subsequent operations. Second, the host performs a series of read and/or write byte operations to the selected register. Four operations are supported on the EPP: Address Write, Data Write, Address Read, and Data Read. All operations on the EPP device are performed asynchronously. 6.2.8.2 EPP Version 1.9 Operation The EPP read/write operation can be completed under the following conditions: a. If the nWait is active low, when the read cycle (nWrite inactive high, nDStrb/nAStrb active low) or write cycle (nWrite active low, nDStrb/nAStrb active low) starts, the read/write cycle proceeds normally and will be completed when nWait goes inactive high. b. If nWait is inactive high, the read/write cycle will not start. It must wait until nWait changes to active low, at which time it will start as described above. 6.2.8.3 EPP Version 1.7 Operation The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive high.
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6.3 Extended Capabilities Parallel (ECP) Port This port is software and hardware compatible with existing parallel ports, so it may be used as a
standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward (host to peripheral) and reverse (peripheral to host) directions. Small FIFOs are used in both forward and reverse directions to improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes. The ECP port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. The ECP port supports run-length-encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Hardware support for compression is optional. For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and ISA Interface Standard. 6.3.1 ECP Register and Mode Definitions NAME data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr ADDRESS Base+000h Base+000h Base+001h Base+002h Base+400h Base+400h Base+400h Base+400h Base+401h Base+402h I/O R/W R/W R R/W R/W R/W R/W R R/W R/W ECP MODES 000-001 011 All All 010 011 110 111 111 All FUNCTION Data Register ECP FIFO (Address) Status Register Control Register Parallel Port Data FIFO ECP FIFO (DATA) Test FIFO Configuration Register A Configuration Register B Extended Control Register
Note: The base addresses are specified by CR23, which are determined by configuration register or hardware setting.
MODE 000 001 010 011 100 101 110 111 SPP mode PS/2 Parallel Port mode Parallel Port Data FIFO mode ECP Parallel Port mode
DESCRIPTION
EPP mode (If this option is enabled in the CR9 and CR0 to select ECP/EPP mode) Reserved Test mode Configuration mode
Note: The mode selection bits are bit 7-5 of the Extended Control Register.
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6.3.2 Data and ecpAFifo Port Modes 000 (SPP) and 001 (PS/2) (Data Port) During a write operation, the Data Register latches the contents of the data bus on the rising edge of the input. The contents of this register are output to the PD0-PD7 ports. During a read operation, ports PD0PD7 are read and output to the host. The bit definitions are as follows: 7 6 5 4 3 2 1 0
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Mode 011 (ECP FIFO-Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is defined only for the forward direction. The bit definitions are as follows:
7
6
5
4
3
2
1
0
Address or RLE
Address/RLE
6.3.3
Device Status Register (DSR)
These bits are at low level during a read of the Printer Status Register. The bits of this status register are defined as follows:
7 6 5 4 3 2 1 1 1 0 1
nFault Select PError nAck nBusy
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Bit 7: This bit reflects the complement of the Busy input. Bit 6: This bit reflects the nAck input. Bit 5: This bit reflects the PError input. Bit 4: This bit reflects the Select input. Bit 3: This bit reflects the nFault input. Bit 2-0: These three bits are not implemented and are always logic one during a read.
6.3.4 Device Control Register (DCR) The bit definitions are as follows:
7 1
6 1
5
4
3
2
1
0
strobe autofd nInit SelectIn ackIntEn Direction
Bit 6, 7: These two bits are logic one during a read and cannot be written. Bit 5: This bit has no effect and the direction is always out if mode = 000 or mode = 010. Direction is valid in all other modes. 0 the parallel port is in output mode. 1 the parallel port is in input mode. Bit 4: Interrupt request enable. When this bit is set to a high level, it may be used to enable interrupt requests from the parallel port to the CPU due to a low to high transition on the ACK# input. Bit 3: This bit is inverted and output to the SLIN# output. 0 The printer is not selected. 1 The printer is selected. Bit 2: This bit is output to the INIT# output. Bit 1: This bit is inverted and output to the AFD# output. Bit 0: This bit is inverted and output to the STB# output.
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6.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 This mode is defined only for the forward direction. The standard parallel port protocol is used by a hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this FIFO. Transfers to the FIFO are byte aligned. 6.3.6 ecpDFifo (ECP Data FIFO) Mode = 011 When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned. When the direction bit is 1, data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to the system. 6.3.7 tFifo (Test FIFO Mode) Mode = 110
Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the parallel port lines. However, data in the tFIFO may be displayed on the parallel port data lines. 6.3.8 cnfgA (Configuration Register A) Mode = 111
This register is a read-only register. When it is read, 10H is returned. This indicates to the system that this is an 8-bit implementation. 6.3.9 cnfgB (Configuration Register B) Mode = 111
The bit definitions are as follows: 7 6 5 4 3 1 2 1 1 0 1
IRQx 0 IRQx 1 IRQx 2 intrValue compress Bit 7: This bit is read-only. It is at low level during a read. This means that this chip does not support hardware RLE compression. Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts.
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Bit 5-3: Reflect the IRQ resource assigned for ECP port. cnfgB[5:3] IRQ resource 000 reflect other IRQ resources selected by PnP register (default) 001 IRQ7 010 IRQ9 011 IRQ10 100 IRQ11 101 IRQ14 110 IRQ15 111 IRQ5 Bit 2-0: These five bits are at high level during a read and can be written. 6.3.10 ecr (Extended Control Register) Mode = all
This register controls the extended ECP parallel port functions. The bit definitions are follows:
7 6 5 4 3 2 1 0
empty full service Intr dmaEn nErrIntrEn MODE MODE MODE
Bit 7-5: These bits are read/write and select the mode. 000 001 Standard Parallel Port mode. The FIFO is reset in this mode. PS/2 Parallel Port mode. This is the same as 000 except that direction may be used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register. Parallel Port FIFO mode. This is the same as 000 except that bytes are written or DMAed to the FIFO. FIFO data are automatically transmitted using the standard parallel port protocol. This mode is useful only when direction is 0. ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and auto transmitted to the peripheral using ECP Protocol. When the direction is 1 (reverse direction), bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. Selects EPP Mode. In this mode, EPP is activated if the EPP mode is selected. Reserved. Test Mode. The FIFO may be written and read in this mode, but the data will not be transmitted on the parallel port. Configuration Mode. The confgA and confgB registers are accessible at 0x400 and 0x401 in this mode. Publication Release Date: Nov. 2000 Revision 0.60
010
011
100 101 110 111
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Bit 4: Read/Write (Valid only in ECP Mode) 1 Disables the interrupt generated on the asserting edge of nFault. 0 Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted (interrupt) an interrupt will be generated and this bit is written from a 1 to 0. Bit 3: Read/Write 1 Enables DMA. 0 Disables DMA unconditionally. Bit 2: Read/Write 1 Disables DMA and all of the service interrupts. 0 Enables one of the following cases of interrupts. When one of the service interrupts has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to 0 to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt. (a) dmaEn = 1: During DMA this bit is set to a 1 when terminal count is reached. (b) dmaEn = 0 direction = 0: This bit is set to 1 whenever there are writeIntr Threshold or more bytes free in the FIFO. (c) dmaEn = 0 direction = 1: This bit is set to 1 whenever there are readIntr Threshold or more valid bytes to be read from the FIFO. Bit 1: Read only 0 The FIFO has at least 1 free byte. 1 The FIFO cannot accept another byte or the FIFO is completely full. Bit 0: Read only 0 The FIFO contains at least 1 byte of data. 1 The FIFO is completely empty. 6.3.11 Bit Map of ECP Port Registers D7 data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr
Notes: 1. These registers are available in all modes. 2. All FIFOs use one common 16-byte FIFO. PD7 Addr/RLE nBusy 1
D6
PD6
D5
PD5
D4
PD4
D3
PD3
D2
PD2
D1
PD1
D0
PD0
NOTE
2
Address or RLE field nAck 1 PError Directio Select ackIntEn nFault SelectIn 1 nInit 1 autofd 1 strobe
1 1 2 2 2
Parallel Port Data FIFO ECP Data FIFO Test FIFO 0 compress 0 intrValue MODE 0 1 1 1 nErrIntrEn 0 1 dmaEn 0 1 serviceIntr 0 1 full 0 1 empty
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6.3.12 ECP Pin Descriptions NAME nStrobe (HostClk) TYPE O DESCRIPTION The nStrobe registers data or address into the slave on the asserting edge during write operations. This signal handshakes with Busy. These signals contains address or data or RLE data. This signal indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse. This signal deasserts to indicate that the peripheral can accept data. It indicates whether the data lines contain ECP command information or data in the reverse direction. When in reverse direction, normal data are transferred when Busy (PeriphAck) is high and an 8-bit command is transferred when it is low. This signal is used to acknowledge a change in the direction of the transfer (asserted = forward). The peripheral drives this signal low to acknowledge nReverseRequest. The host relies upon nAckReverse to determine when it is permitted to drive the data bus. Indicates printer on line. Requests a byte of data from the peripheral when it is asserted. This signal indicates whether the data lines contain ECP address or data in the forward direction. When in forward direction, normal data are transferred when nAutoFd (HostAck) is high and an 8-bit command is transferred when it is low. Generates an error interrupt when it is asserted. This signal is valid only in the forward direction. The peripheral is permitted (but not required) to drive this pin low to request a reverse transfer during ECP Mode. This signal sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. This signal is always deasserted in ECP mode.
PD<7:0> nAck (PeriphClk) Busy (PeriphAck)
I/O I I
PError (nAckReverse)
I
Select (Xflag) nAutoFd (HostAck)
I O
nFault (nPeriphRequest)
I
nInit (nReverseRequest)
O
nSelectIn (ECPMode)
O
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6.3.13 ECP Operation The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol before ECP operation. After negotiation, it is necessary to initialize some of the port bits. The following are required: (a) Set direction = 0, enabling the drivers. (b) Set strobe = 0, causing the nStrobe signal to default to the deasserted state. (c) Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state. (d) Set mode = 011 (ECP Mode) ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo, respectively. 6.3.13.1 Mode Switching Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (mode 011 or 010). If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. The direction can be changed only in mode 001. When in extended forward mode, the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In ECP reverse mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001. 6.3.13.2 Command/Data ECP mode allows the transfer of normal 8-bit data or 8-bit commands. In the forward direction, normal data are transferred when HostAck is high and an 8-bit command is transferred w hen HostAck is low. The most significant bits of the command indicate whether it is a run-length count (for compression) or a channel address. In the reverse direction, normal data are transferred when PeriphAck is high and an 8 -bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero. 6.3.13.3 Data Compression The W83627SF supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported. In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo. 6.3.14 FIFO Operation
The FIFO threshold is set in configuration register 5. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO is disabled.
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6.3.15 DMA Transfers DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. The DMA uses the standard PC DMA services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted, which will disable the DMA. 6.3.16 Programmed I/O (NON-DMA) Mode
The ECP or parallel port FIFOs can also be operated using interrupt driven programmed I/O. Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. The host must set the direction, state, dmaEn = 0 and serviceIntr = 0 in the programmed I/O transfers. The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode.
6.4 Extension FDD Mode (EXTFDD)
In this mode, the W83627SF changes the printer interface pins to FDC input/output pins, allowing the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin assignments for the FDC input/output pins are shown in Table 6-1. After the printer interface is set to EXTFDD mode, the following occur: (1) Pins MOB# and DSB# will be forced to inactive state. (2) Pins DSKCHG#, RDATA#, WP#, TRAK0#, INDEX# will be logically ORed with pins PD4-PD0 to serve as input signals to the FDC. (3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for FDD open drain/collector output. (4) If the parallel port is set to EXTFDD mode after the system has booted DOS or another operating system, a warm reset is needed to enable the system to recognize the extension floppy drive.
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6.5 Extension 2FDD Mode (EXT2FDD)
In this mode, the W83627SF changes the printer interface pins to FDC input/output pins, allowing the user to install two external floppy disk drives through the DB-25 printer connector to replace internal floppy disk drives A and B. The pin assignments for the FDC input/output pins are shown in Table6-1. After the printer interface is set to EXTFDD mode, the following occur: (1) Pins MOA#, DSA#, MOB#, and DSB# will be forced to inactive state. (2) Pins DSKCHG#, RDATA#, WP#, TRAK0#, and INDEX# will be logically ORed with pins PD4-PD0 to serve as input signals to the FDC. (3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for FDD open drain/collector output. (4) If the parallel port is set to EXT2FDD mode after the system has booted DOS or another operating system, a warm reset is needed to enable the system to recognize the extension floppy drive.
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PRELIMINARY 7. KEYBOARD CONTROLLER
The KBC (8042 with licensed KB BIOS) circuit of W83627SF is designed to provide the functions needed to interface a CPU with a keyboard and/or a PS/2 mouse, and can be used with IBM(R)-compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. Then, The controller will asserts an interrupt to the system when data are placed in its output buffer. The keyboard and PS/2 mouse are required to acknowledge all data transmissions. No transmission should be sent to the keyboard or PS/2 mouse until an acknowledge is received for the previous data byte.
P24 P25 P21 KINH P17 P20 P27
KIRQ MIRQ GATEA20 KBRST KDAT KCLK
8042
GP I/O PINS Multiplex I/O PINS
P10 P26 T0
P12~P16
P23 T1 P22 P11
MCLK
MDAT
Keyboard and Mouse Interface
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7.1 Output Buffer
The output buffer is an 8 -bit read-only register at I/O address 60H (Default, PnP programmable I/O address LD5-CR60 and LD5-CR61). The keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by commands to the system. The output buffer can only be read when the output buffer full bit in the register is "1".
7.2 Input Buffer
The input buffer is an 8-bit write-only register at I/O address 60H or 64H (Default, PnP programmable I/O address LD5-CR60, LD5-CR61, LD5-CR62, and LD5-CR63). Writing to address 60H sets a flag to indicate a data write; writing to address 64H sets a flag to indicate a command write. Data written to I/O address 60H is sent to keyboard (unless the keyboard controller is expecting a data byte) through the controller's input buffer only if the input buffer full bit in the status register is "0".
7.3 Status Register
The status register is an 8 -bit read-only register at I/O address 64H (Default, PnP programmable I/O address LD5-CR62 and LD5-CR63), that holds information about the status of the keyboard controller and interface. It may be read at any time. BIT 0 1 2 BIT FUNCTION Output Buffer Full Input Buffer Full System Flag DESCRIPTION 0: Output buffer empty 1: Output buffer full 0: Input buffer empty 1: Input buffer full This bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller. It defaults to 0 after a power-on reset. 0: Data byte 1: Command byte 0: Keyboard is inhibited 1: Keyboard is not inhibited 0: Auxiliary device output buffer empty 1: Auxiliary device output buffer full 0: No time-out error 1: Time-out error 0: Odd parity 1: Even parity (error)
3 4 5 6 7
Command/Data Inhibit Switch Auxiliary Device Output Buffer General Purpose Timeout Parity Error
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7.4 Commands
COMMAND 20h 60h FUNCTION Read Command Byte of Keyboard Controller Write Command Byte of Keyboard Controller
BIT 7 6 5 4 3 2 1 0 Reserved IBM Keyboard Translate Mode Disable Auxiliary Device Disable Keyboard Reserve System Flag Enable Auxiliary Interrupt Enable Keyboard Interrupt BIT DEFINITION
A4h
Test Password Returns 0Fah if Password is loaded Returns 0F1h if Password is not loaded
A5h
Load Password Load Password until a "0" is received from the system
A6h
Enable Password Enable the checking of keystrokes for a match with the password
A7h A8h A9h
Disable Auxiliary Device Interface Enable Auxiliary Device Interface Interface Test
BIT 00 01 02 03 04 BIT DEFINITION No Error Detected Auxiliary Device "Clock" line is stuck low Auxiliary Device "Clock" line is stuck high Auxiliary Device "Data" line is stuck low Auxiliary Device "Data" line is stuck low
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7.4 Commands, continued COMMAND AAh Self-test Returns 055h if self test succeeds ABh Interface Test
BIT 00 01 02 03 04 BIT DEFINITION No Error Detected Keyboard "Clock" line is stuck low Keyboard "Clock" line is stuck high Keyboard "Data" line is stuck low Keyboard "Data" line is stuck high
FUNCTION
ADh AEh C0h C1h C2h D0h D1h D2h D3h D4h E0h FXh
Disable Keyboard Interface Enable Keyboard Interface Read Input Port(P1) and send data to the system Continuously puts the lower four bits of Port1 into STATUS register Continuously puts the upper four bits of Port1 into STATUS register Send Port2 value to the system Only set/reset GateA20 line based on the system data bit 1 Send data back to the system as if it came from Keyboard Send data back to the system as if it came from Auxiliary Device Output next received byte of data from system to Auxiliary Device Reports the status of the test inputs Pulse only RC(the reset line) low for 6S if Command byte is even
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7.5 HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC
The KBC implements a hardware control logic to speed-up GATEA20 and KBRESET. This control logic is controlled by LD5-CRF0 as follows: 7.5.1 KB Control Register (Logic Device 5, CR-F0) BIT NAME 7 KCLKS1 6 KCLKS0 5 Reserved 4 Reserved 3 Reserved 2 P92EN 1 HGA20 0 HKBRST
KCLKS1, KCLKS0 This 2 bits are for the KBC clock rate selection. =00 KBC clock input is 6 Mhz =01 KBC clock input is 8 Mhz =10 KBC clock input is 12 Mhz =11 KBC clock input is 16 Mhz P92EN (Port 92 Enable) A "1" on this bit enables Port 92 to control GATEA20 and KBRESET. A "0" on this bit disables Port 92 functions. HGA20 (Hardware GATE A20) A "1" on this bit selects hardware GATEA20 control logic to control GATE A20 signal. A "0" on this bit disables hardware GATEA20 control logic function. HKBRST (Hardware Keyboard Reset) A "1" on this bit selects hardware KB RESET control logic to control KBRESET signal. A "0" on this bit disable hardware KB RESET control logic function. When the KBC receives a data follows a "D1" command, the hardware control logic sets or clears GATE A20 according to the received data bit 1. Similarly, the hardware control logic sets or clears KBRESET depending on the received data bit 0. When the KBC receives a "FE" command, the KBRESET is pulse low for 6S(Min.) with 14S(Min.) delay. GATEA20 and KBRESET are controlled by either the software control or the hardware control logic and they are mutually exclusive. Then, GATEA20 and KBRESET are merged along with Port92 when P92EN bit is set. 7.5.2 Port 92 Control Register (Default Value = 0x24) BIT NAME 7 Res. (0) 6 Res. (0) 5 Res. (1) 4 Res. (0) 3 Res. (0) 2 Res. (1) 1 SGA20 0 PLKBRST
SGA20 (Special GATE A20 Control) A "1" on this bit drives GATE A20 signal to high. A "0" on this bit drives GATE A20 signal to low. PLKBRST (Pull-Low KBRESET) A "1" on this bit causes KBRESET to drive low for 6 S(Min.) with 14S(Min.) delay. Before issuing another keyboard reset command, the bit must be cleared.
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PRELIMINARY 8. GENERAL PURPOSE I/O
W83627SF provides 42 input/output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. These 42 GP I/O ports are divided into seven groups. GP1 is configured through control registers in logical device 7, GP2 in logical device 8, GP3 and GP4 in logical device 9, GP5, GP6, and GP7 in logical device C. Users can configure each individual port to be an input or output port by programming respective bit in I/O selection register (0 = output, 1 = input). Invert port value by setting inversion register (0 = non-inverse, 1 = inverse). Port v alue is read/written through data register. Table 8.1 and 8.2 gives more details on GPIO's assignment. In addition, GP3 and GP4 are designed to be functional even in power loss condition (VCC is off). Figure 8.1 shows the GP I/O port's structure. Right after Power-on reset, those ports default to perform basic input function
except ports in GP3 and GP4 which maintain their previous settings until a battery loss condition. Table 8.1 SELECTION BIT 0 = OUTPUT 1 = INPUT 0 0 1 1 INVERSION BIT 0 = NON INVERSE 1 = INVERSE 0 1 0 1 Basic non-inverting output Basic inverting output Basic non-inverting input Basic inverting input BASIC I/O OPERATIONS
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Table 8.2 GP I/O PORT DATA REGISTER REGISTER BIT ASSIGNMENT BIT 0 BIT 1 BIT 2 BIT 3 GP1 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 GP2 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 GP3 BIT 2 BIT 3 BIT 4 BIT 5 BIT 0 GP4 BIT 1 BIT 2 GP I/O PORT GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 GP20 GP21 GP22 GP23 GP24 GP25 GP26 GP27 GP30 GP31 GP32 GP33 GP34 GP35 GP40 GP41 GP42
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Table 8.2, continued GP I/O PORT DATA REGISTER REGISTER BIT ASSIGNMENT BIT 0 BIT 1 BIT 2 BIT 3 GP5 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 GP6 BIT 2 BIT 3 BIT 0 BIT 1 GP7 BIT 2 BIT 3 BIT 4 GP I/O PORT GP50 GP51 GP52 GP53 GP54 GP55 GP56 GP57 GP60 GP61 GP62 GP63 GP70 GP71 GP72 GP73 GP74
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PRELIMINARY
Figure 8.1
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PRELIMINARY 9. PLUG AND PLAY CONFIGURATION
The W83627SF uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83627SF, there are twelve Logical Devices (from Logical Device 0 to Logical Device C with the exception of logical device 4 for backward compatibility) which correspond to eleven individual functions: FDC (logical device 0), PRT (logical device 1), UART A (logical device 2), UART B (logical device 3), KBC (logical device 5), CIR (Consumer IR, logical device 6), GP1 (logical device 7), GP2 (logical device 8), GP3 and GP4 (logical device 9), ACPI ((logical device A), Smart Card interface (logical device B), and GP5, GP6, and GP7 (logical device C). Each Logical Device has its own
configuration registers (above CR30). Host can access those registers by writing an appropriate logical device number into logical device select register at CR07.
9.1 Compatible PnP
9.1.1 Extended Function Registers In Compatible PnP, there are two ways to enter Extended Function and read or write the configuration registers. HEFRAS (CR26 bit 6) can be used to select one out of these two methods of entering the Extended Function mode as follows: HEFRAS 0 1 address and value write 87h to the location 2Eh twice write 87h to the location 4Eh twice
After Power-on reset, the value on RTSA# (pin 43) is latched by HEFRAS of CR26. In Compatible PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port address 2Eh or 4Eh). Secondly, an index value (02h, 07h-FFh) must be written to the Extended Functions Index Register (I/O port address 2Eh or 4Eh same as Extended Functions Enable Register) to identify which
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configuration register is to be accessed. The designer can then access the desired configuration
register through the Extended Functions Data Register (I/O port address 2Fh or 4Fh). After programming of the configuration register is finished, an additional value (AAh) should be written to EFERs to exit the Extended Function mode to prevent unintentional access to those configuration registers. The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the configuration registers against accidental accesses. The configuration registers can be reset to their default or hardware settings only by a cold reset (pin MR = 1). A warm reset will not affect the configuration registers. 9.1.2 Extended Functions Enable Registers (EFERs) After a power-on reset, the W83627SF enters the default operating mode. Before the W83627SF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function
Enable Registers are write-only registers. On a PC/AT system, their port addresses are 2Eh or 4Eh (as described in previous section). 9.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) After the extended function mode is entered, the Extended Function Index Register (EFIR) must be loaded with an index value (02h, 07h-FEh) to access Configuration Register 0 (CR0), Configuration Register 7 (CR07) to Configuration Register FE (CRFE), and so forth through the Extended Function Data Register (EFDR). The EFIRs are write-only registers with port address 2Eh or 4Eh (as described in section 12.2.1) on PC/AT systems; the EFDRs are read/write registers with port address 2Fh or 4Fh (as described in section 9.2.1) on PC/AT systems.
9.2 Configuration Sequence
To program W83627SF configuration registers, the following configuration sequence must be followed: (1). Enter the extended function mode (2). Configure the configuration registers (3). Exit the extended function mode 9.2.1 Enter the extended function mode To place the chip into the extended function mode, two successive wrtites of 0x87 must be applied to Extended Function Enable Registers(EFERs, i.e. 2Eh or 4Eh). Publication Release Date: Nov. 2000 Revision 0.60
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9.2.2 Configurate the configuration registers The chip selects the logical device and activates the desired logical devices through Extended Function Index Register(EFIR) and Extended Function Data Register(EFDR). EFIR is located at the same address as EFER, and EFDR is located at address (EFIR+1). First, write the Logical Device Number (i.e.,0x07) to the EFIR and then write the number of the desired logical device to the EFDR. If accessing the Chip(Global) Control Registers, this step is not required. Secondly, write the address of the desired configuration register within the logical device to the EFIR and then write (or read) the desired configuration register through EFDR.
9.2.3 Exit the extended function mode To exit the extended function mode, one w rite of 0xAA to EFER is required. Once the chip exits the extended function mode, it is in the normal running mode and is ready to enter the configuration mode.
9.2.4 Software programming example The following example is written in Intel 8086 assembly language. It assumes that the EFER is located at 2Eh, so EFIR is located at 2Eh and EFDR is located at 2Fh. If HEFRAS (CR26 bit 6) is set, 4Eh can be directly replaced by 4Eh and 2Fh replaced by 4Fh. ;----------------------------------------------------------------------------------; Enter the extended function mode ,interruptible double-write ;----------------------------------------------------------------------------------MOV MOV OUT OUT DX,2EH AL,87H DX,AL DX,AL |
;----------------------------------------------------------------------------; Configurate logical device 1, configuration register CRF0 | ;----------------------------------------------------------------------------MOV MOV OUT MOV DX,2EH AL,07H DX,AL DX,2FH ; point to Logical Device Number Reg.
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MOV OUT ; MOV MOV OUT MOV MOV OUT DX,2EH AL,F0H DX,AL DX,2FH AL,3CH DX,AL ; update CRF0 with value 3CH ; select CRF0 AL,01H DX,AL ; select logical device 1
;-----------------------------------------; Exit extended function mode ;-----------------------------------------MOV MOV OUT DX,2EH AL,AAH DX,AL |
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PRELIMINARY 10. ACPI REGISTERS FEATURES
W83627SF supports both ACPI and legacy power managements. The switch logic of the power management block generates an SMI# interrupt in the legacy mode and an PME# interrupt in the ACPI mode. The new ACPI feature routes SMI#/PME# logic output either to SMI# or to PME#.The SMI#/PME# logic routes to SMI# only when both PME_EN = 0 and SMIPME_OE = 1. Similarly, the SMI#/PME# logic routes to PME# only when both PME_EN = 1 and SMIPME_OE = 1.
PME_EN IRQ events
SMIPME_OE
SMI / PME Logic 0
SMI
1
SMIPME_OE
PME
Device Idle Timers Device Trap Global STBY Timer
IRQs
Sleep/Wake State machine
WAK_STS Clock Control
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PRELIMINARY 11. SMART CARD INTERFACE
Because of similarity of transmission protocol to UART, the register map of Smart Card interface of Winbond I/O is designed to be UART-like for easy programming. Details of these registers are described as follows.
11.1 Receiver Buffer Register (RBR, read only at "base address + 0" when BDLAB = 0)
Data from IC card are buffered in this register for host to read.
11.2 Transmitter Buffer Register (TBR, write only at "base address + 0" when BDLAB = 0)
Host writes to this register to send data to IC card.
11.3 Interrupt Control Register (ICR, at "base address + 1" when BDLAB = 0)
This 8-bit register allows the four types of interrupts. The interrupt system can be completely disabled by resetting bits 0 through 4 of the Interrupt Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this register to a logical 1.
7 0 6 0 5 0 4 3 0 Enable RBR Data Ready Interrupt (ERDRI) Enable TBR Empty Interrupt (ETBREI) Enable SSR Interrupt (ESSRI) Enabel SCPSNT Interrupt (ESCPTI) 2 1 0
Bit 7-5: These bits are always logic 0. Bit 4: ESCPTI. Setting this bit to a logical 1 enables SCPSNT interrupt when a card is inserted. Bit 3: This bit is always logic 0. Bit 2: ESSRI. Setting this bit to a logical 1 enables Smart Card interface status register interrupt. Bit 1: ETBREI. Setting this bit to a logical 1 enables TBR empty interrupt. Bit 0: ERDRI. Setting this bit to a logical 1 enables RBR data ready interrupt.
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11.4 Interrupt Status Register (ISR, read only at "base address + 2")
This register reflects the Smart Card interface interrupt status, which is encoded by different interrupt sources into 4 bits.
7 6 5 4 3 2 1 0 No interrupt pending Interrupt status bit 0 Interrupt status bit 0 Interrupt status bit 0 SCPSNT toggle Interrupt (SCPTI) SCPSNT line status FIFO enabled FIFO enabled
Bit 7, 6: These two bits are set to a logical 1 when SFR bit 0 = 1. Bit 5: Reflect value of SCPSNT line status. Bit 4: Set to 1 if SCPSNT toggles when this type of interrupt is enabled. Bit 0 of this register is also set to 0 if this type of interrupt occurs. Bit 3 - 1: These three bits identify the priority level of the pending interrupt, as shown in the table below. Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred, this bit will be set to a logical 0. INTERRUPT CONTROL FUNCTION ISR
Bit 3 0 0 Bit 2 0 1 Bit 1 0 1 Bit 0 1 0 Interrupt priority First Interrupt Type Smart Card interface Receive Status RBR Data Ready
INTERRUPT SET AND FUNCTION
Interrupt Source No Interrupt pending 1. OER = 1 2. PBER =1 Read SCSR 3. NSER = 1 4. SBD = 1 1. RBR data ready 2. FIFO interrupt active level reached 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR Clear Interrupt -
0
1
0
0
Second
1
1
0
0
Second
FIFO Data Timeout
Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. TBR empty
0
0
1
0
Third
TBR Empty
1. Write data into TBR 2. Read ISR (if priority is third)
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11.5 Smart Card FIFO Control Register (SCFR, write only at "base address + 2")
This register is used to control the FIFO functions of Smart Card interface.
7 6 5 4 3 2 1 0 FIFO enable Receiver FIFO reset Transmitter FIFO reset RX interrupt active level (LSB) RX interrupt active level (MSB)
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO. FIFO TRIGGER LEVEL BIT 7 0 0 1 1 BIT 6 0 1 0 1 RX FIFO INTERRUPT ACTIVE LEVEL (BYTES) 01 04 08 14
Bit 5 - 3: Reserved. Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will be cleared to a logical 0 by itself after being set to a logical 1. Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will be cleared to a logical 0 by itself after being set to a logical 1. Bit 0: This bit enables FIFO of Smart Card interface. This bit should be set to a logical 1 before other bits of SCFR are programmed.
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11.6 Smart Card Control Register (SCCR, write only at "base address + 3")
The Smart Card Control Register controls and defines the parity bit protocol for asynchronous data communications.
7 6 0 5 0 4 3 2 0 1 1 0 1 Parity Bit Enable (PBE) Even Parity Enable (EPE) Baud rate Divisor Latch Access Bit (BDLAB)
Bit 7: BDLAB. When this bit is set to a logical 1 designers can access the divisor (in 16-bit binary , format) from the divisor latches of the baudrate generator during a read or write operation. When this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the Interrupt Control Register can be accessed. Bit 6 - 5: Reserved. Always 0 when read. Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit 3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. When the bit is reset, an odd number of logic 1's are sent or checked. Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT will be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same position as the transmitter will be detected. Bit 2 - 0: Reserved. Bit 2 is always 0 and bit 1 - 0 are always 1 when read.
11.7 Interrupt Enable Register (IER, at "base address + 4")
This register contains global interrupt enable bit of Smart Card interface.
7 0 6 0 5 0 4 0 3 2 0 1 0 0 0 IRQ enable
Bit 7 - 4: Reserved. Always 0 when read. Bit 3: The Smart Card interface interrupt output is enabled by setting this bit to a logic 1. Bit 2 - 0: Reserved. Always 0 when read. Publication Release Date: Nov. 2000 Revision 0.60
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11.8 Smart Card Status Register (SCSR, at "base address + 5")
This 8-bit register provides information about the status of the data transfer during communication.
7 6 5 4 3 2 1 0 RBR Data Ready (RDR) Overrun Error (OER) Parity Bit Error (PBER) No Stop bit Error (NSER) Silent Byte Detected (SBD) Transmitter Buffer Register Empty (TBRE) Transmitter Shift Register Empty (TSRE ) RX FIFO Error Indication (RFEI)
Bit 7: RFEI. This bit is set to a logic 1 when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO. It is cleared by reading SCSR until there are no remaining errors left in the FIFO. Bit 6: TSRE. If the transmitting FIFO and TSR are both empty, it will be set to a logical 1. Otherwise, this bit will be reset to a logical 0. Bit 5: TBRE. When a data character is transferred from TBR to TSR, this bit will be set to a logical 1. If ETBREI of ICR is a logical 1, an interrupt will be generated to notify the CPU to write the next data. It will be reset to a logical 0 when CPU writes data into TBR or FIFO. Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full word time, including start bit, data bits, parity bit, and stop bits. When the CPU reads SCSR, it will clear this bit to a logical 0. Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. When CPU reads SCSR, it will clear this bit to a logical 0. Bit 2: PBER. This bit is set to a logical 1 to indicate that parity bit of received data is incorrect. When CPU reads SCSR, it will clear this bit to a logical 0. Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next received data before they were read by CPU. When CPU reads USR, it will clear this bit to a logical 0. Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by CPU in the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.
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11.9 Extended Control Register (ECR, at "base address + 7")
This 8-bit register provides control settings for Smart Card interface.
7 6 5 4 3 2 1 0 Warm reset SCIO direction CLKSTP CLKSTPH SCCLK frequency select bit 0 SCCLK frequency select bit 1 Internal sampling clock base select bit 0 Internal sampling clock base select bit 1
Bit 7 - 6: These two bits (BASESEL1 and BASESEL0 respectively) select internal sampling clock base multiplier versus baud rate. BASESEL1, BASESEL0 multiplier 00 01 10 11 14x 16x 18x 16x
Bit 5 - 4: These two bits (CLKSEL1 and CLKSEL0 respectively) select frequency of SCCLK. CLKSEL1, CLKSEL0 SCCLK frequuency 00 01 10 11 1.5 MHz 3 MHz 6 MHz 12 MHz
Bit 3: CLKSTPH. This bit determines SCCLK stuck at high or low after CLKSTP is set to 1. SCCLK stays high if CLKSTPH is equal to 1 and stays low otherwise. Bit 2: CLKSTP. Setting this bit to 1 will stop SCCLK. Bit 1: SCDIR. This bit determine direction of SCIO pin. SCIO serves as an input port if SCDIR is 1. It is an output port if SCDIR is 0. Bit 0: WRST. Writing a 1 to this bit issues a warm reset to IC card. It is self-cleared after writing a 1.
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11.10 Baud rate divisor Latch High and Baud rate divisor Latch Low (BHL and BLL at "base address + 1" and "base address + 0" respectively when BDLAB = 1)
Combining with BASESEL1 and BASESEL0 of ECR, these two bytes of registers provide user all the possible combinations to cover all the available settings regarding clock rate conversion factor and baud rate adjustment factor.
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Smart Card interface register bit map. Bit Number
Register Address Base +0 BDLAB = 0 Receiver Buffer Register (Read Only) RBR 0 RX Data Bit 0 1 RX Data Bit 1 2 RX Data Bit 2 3 RX Data Bit 3 4 RX Data Bit 4 5 RX Data Bit 5 6 RX Data Bit 6 7 RX Data Bit 7
+0 Transmitter BDLAB = 0 Buffer Register (Write Only) +1 Interrupt Control Register BDLAB = 0
TBR
TX Data Bit 0 RBR Data Ready Interrupt Enable (ERDRI) "0" if Interrupt Pending
TX Data Bit 1 TBR Empty Interrupt Enable (ETBREI) Interrupt Status Bit (0)
TX Data Bit 2 SSR INTERRUPT ENABLE (EUSRI) Interrupt Status Bit (1)
TX Data Bit 3 0
TX Data Bit 4 SCPSNT toggle interrupt Enable (ESCPTI) SCPSNT toggle interrupt status (SCPTI) Reserved
TX Data Bit 5 0
TX Data Bit 6 0
TX Data Bit 7 0
ICR
+2
Interrupt Status Register (Read Only)
ISR
Interrupt Status Bit (2)
SCPSNT line status
FIFOs Enabled **
FIFOs Enabled **
+2
SMART CARD FIFO Control Register (Write Only) SMART CARD Control Register
SCFR
FIFO Enable
RCVR FIFO Reset
XMIT FIFO Reset
Reserved
Reversed
RX RX Interrupt Interrupt Active Level Active Level (LSB) (MSB) 0 Baudrate Divisor Latch Access Bit (BDLAB) 0 RX FIFO Error Indication (RFEI) Internal sampling clock base select 1 Bit 7
+3
SCCR
1
1
0
Parity Bit Enable (PBE) IRQ Enable No Stop Bit Error (NSER) CLKSTPH
Even Parity Enable (EPE) 0 SILENT BYTE DETECTED (SBD) SCCLK frequency select 0 Bit 4
0
+4 +5
Interrupt Enable Register SMART CARD Status Register Reserved Extended Control Register
IER SCSR
0 RBR Data Ready (RDR)
0 Overrun Error (OER)
0 Parity Bit Error (PBER)
0 TBR Empty (TBRE)
0 TSR Empty (TSRE)
+6 +7
ECR
Warm reset
SCIO direction
CLKSTP
SCCLK frequency select 1 Bit 5
Internal sampling clock base select 0 Bit 6
+0 BDLAB = 1 +1 BDLAB = 1
Baudrate Divisor Latch Low Baudrate Divisor Latch High
BLL
Bit 0
Bit 1
Bit 2
Bit 3
BHL
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
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PRELIMINARY 12. SERIAL IRQ
W83627SF supports a serial IRQ scheme. This allow a signal line to be used to report the legacy ISA interrupt rerquests. Because more than one device may need to share the signal serial IRQ signal line, an open drain signal scheme is used. The clock source is the PCI clock. The serial interrupt is
transfered on the IRQSER signal, one cycle consisting of three frames types: a start frame, several IRQ/Data frame, and one Stop frame. 12.1 Start Frame There are two modes of operation for the IRQSER Start frame: Quiet mode and Continuous mode. In the Quiet mode, the peripheral drives the SERIRQ signal active low for one clock, and then tri-states it. This brings all the states machines of the peripherals from idle to active states. The host controller will then take over driving IRQSER signal low in the next clock and will continue driving the IRQSER low for programmable 3 to 7 clock periods. This makes the total number of clocks low for 4 to 8 clock periods. After these clocks, the host controller will drive the IRQSER high for one clock and then tristates it. In the Continuous mode, only the host controller initiates the START frame to update IRQ/Data line information. The host controller drives the IRQSER signal low for 4 to 8 clock periods. Upon a reset, the IRQSER signal is defaulted to the Continuous mode for the host controller to initiate the first Start frame.
12.2 IRQ/Data Frame Once the start frame has been initiated, all the peripherals must start counting frames based on the rsing edge of the start pulse. Each IRQ/Data Frame is three clocks long: Sample phase, Recovery phase, and Turn-around phase. During the Sample phase, the peripheral drives SERIRQ low if the corresponding IRQ is active. If the corresponding IRQ is inactive, then IRQSER must be left tri-stated. During the Recovery phase, the peripheral device drives the IRQSER high. During the Turn-around phase, the peripheral device left the IRQSER tri-stated. The IRQ/Data Frame has a number of specific order, as shown in Table 3-1.
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Table 12-2 IRQSER Sampling periods IRQ/Data Frame 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 32:22 Signal Sampled IRQ0 IRQ1 SMI# IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK# INTA# INTB# INTC# INTD# Unassigned # of clocks past Start 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 95
12.3 Stop Frame
After all IRQ/Data Frames have completed, the host controller will terminate IRQSER by a Stop frame. Only the host controller can initiate the Stop frame by driving IRQSER low for 2 or 3 clocks. If the Stop Frame is low for 2 clocks, the next IRQSER cycle's Sample mode is the Quiet mode. If the Stop Frame is low for 3 clocks, the next IRQSER cycle's Sample mode is the Continuous mode.
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PRELIMINARY 13. CONFIGURATION REGISTER
13.1 Chip (Global) Control Register
CR02 (Default 0x00) Bit 7 - 1 : Reserved. Bit 0 : SWRST --> Soft Reset. CR07 Bit 7 - 0 : LDNB7 - LDNB0 --> Logical Device Number Bit 7 - 0 CR20 Bit 7 - 0 : DEVIDB7 - DEBIDB0 --> Device ID Bit 7 - Bit 0 = 0x59 (read only). CR21 Bit 7 - 0 : DEVREVB7 - DEBREVB0 --> Device Rev Bit 7 - Bit 0 = 0x5v (read only, v is version number). CR22 (Default 0xff) Bit 7 : Reserved. Bit 6 : HMPWD. Hardware monitor power down enable. = 0 Power down = 1 No Power down Bit 5 : URBPWD. UART B power down enable. = 0 Power down = 1 No Power down Bit 4 : URAPWD. UART A power down enable. = 0 Power down = 1 No Power down Bit 3 : PRTPWD. Printer port power down enable. = 0 Power down = 1 No Power down Bit 2 : Reserved. Bit 1 : SCPWD. Smart card interface power down enable. = 0 Power down = 1 No Power down Bit 0 : FDCPWD. FDC power down enable. = 0 Power down = 1 No Power down
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CR23 (Default 0x00) Bit 7 - 1 : Reserved. Bit 0 : IPD (Immediate Power Down). When set to 1, it will put the whole chip into power down mode immediately. CR24 (Default 0b1s000s0s) Bit 7 Bit 6 : Reserved. : CLKSEL = 0 The clock input on Pin 1 should be 24 Mhz. = 1 The clock input on Pin 1 should be 48 Mhz. The corresponding power-on setting pin is SOUTB (pin 83). Bit 5 - 3 : Reserved. Bit 2 : ENKBC = 0 KBC is disabled after hardware reset. = 1 KBC is enabled after hardware reset. This bit is read only, and set/reset by power-on setting pin. The corresponding power-on setting pin is SOUTA (pin 54). Bit 1 : Reserved Bit 0 : PNPCSV = 0 The Compatible PnP address select registers have default values. = 1 The Compatible PnP address select registers have no default value. When trying to make a change to this bit, new value of PNPCVS must be complementary to the old one to make an effective change. For example, the user must set PNPCSV to 0 first and then reset it to 1 to reset these PnP registers if the present value of PNPCSV is 1. The corresponding power-on setting pin is NDTRA (pin 52). CR25 (Default 0x00) This register contains enable bit for tri-state device's output pins when corresponding power down enable bit (specified in CR24) is set. Bit 7 - 6 : Reserved Bit 5 : URBTRI. For UART B device. Bit 4 : URATRI. For UART A device. Bit 3 : PRTTRI. For printer port device. Bit 2 : Reserved. Bit 1 : SCTRI. For Smart Card interface. Bit 0 : FDCTRI. For FDC device.
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CR26 (Default 0b0s000000) Bit 7 : SEL4FDD = 0 Select two FDD mode. = 1 Select four FDD mode. Bit 6 : HEFRAS This bit defines how to enable Configuration mode. The corresponding power-on setting pin is NRTSA (pin 51). = 0 Write 87h to the location 2Eh twice. = 1 Write 87h to the location 4Eh twice. Bit 5 : LOCKREG = 0 Enable R/W Configuration Registers. = 1 Disable R/W Configuration Registers. Bit 4 :Reserve Bit 3 : DSFDLGRQ = 0 Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effective on selecting IRQ. = 1 Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not effective on selecting IRQ. Bit 2 : DSPRLGRQ = 0 Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on selecting IRQ. = 1 Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effective on selecting IRQ. Bit 1 : DSUALGRQ = 0 Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ. = 1 Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ. Bit 0 : DSUBLGRQ = 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ. = 1 Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ.
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CR28 (Default 0x00) Bit 7 - 3 : Reserved. Bit 2 - 0 : PRTMODS2 - PRTMODS0 = 0xx Parallel Port Mode = 100 Reserved = 101 External FDC Mode = 110 Reserved = 111 External two FDC Mode CR29 (GPIO3 multiplexed pin selection register. VBAT powered. Default 0x00) Bit 7 : PIN64S = 0 SUSLED (SUSLED control bits are in CRF3 of Logical Device 9) = 1 GP35 Bit 6 : PIN69S = 00 CIRRX# = 01 GP34 Bit 5 : PIN70S = 0 RSMRST# = 1 GP33 Bit 4 : PIN71S = 0 PWROK = 1 GP32 Bit 3 : PIN72S = 0 PWRCTL# = 1 GP31 Bit 2 : PIN 73S = 0 SLP_SX# = 1 GP30 Bit 1 : Reserved. Bit 0 : PIN103S = 0 Pin 103 and pin 104 function as GP41 and GP40 respectively. =1 Pin 103 is S5# signal input signal and pin 104 is system S3 state power control signal. The corresponding power on setting pin is GP42 (pin 102). Its value is latched on the rising edge of internal RSMRST# signal (delay of rising edge of Internal RSMRST# signal from VSB on is half way of that of external RSMRST# pin). The S3 state power control pin (pin 104) outputs low when VSB is on. It outputs high following the falling edge of SLP_SX# (pin 73) signal falling edge. Then it is reset by the falling edge of S5# signal (pin 103). *Note: The falling edge of PWRCTL# signal (pin 72) is delayed an additional 5ms from the falling edge of SLP_SX# signal for supporting STR (Suspend To RAM) function.
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CR2A (GPIO multiplexed pin selection register 1. VCC powered. Default 0X7C) Bit 7 : Port Select (select Game Port or General Purpose I/O Port 1) = 0 Game Port = 1 Enable bit 6 - 2 selection between GP10 ~ GP14 or 8042 KBC P12 - P16 for pin 128 - 124. Bit 6 : PIN128S = 0 8042 P12 = 1 GP10 Bit 5 : PIN127S = 0 8042 P13 = 1 GP11 Bit 4 : PIN126S = 0 8042 P14 = 1 GP12 Bit 3 : PIN125S = 0 8042 P15 = 1 GP13 Bit 2 : PIN124S = 0 8042 P16 = 1 GP14 Bit 1 : PIN120S = 0 MSO (MIDI Serial data Output) = 1 IRQIN0 (select IRQ resource through CRF3 bit 3 - 0 of Logical Device 8) Bit 0 : PIN119S = 0 MSI (MIDI Serial data Input) = 1 GP20 CR2B (GPIO multiplexed pin selection register 2. VCC powered. Default 0xC0) Bit 7 - 6 : Reserved Bit 5 : PIN90S = 0 PLED (PLED0 control bits are in CRF5 bit 7 - 6 of Logical Device 8) = 1 GP23 Bit 4 : PIN89S = 0 WDTO (Watch Dog Timer is controlled by CRF5, CRF6, CRF7 of Logical Device 8) = 1 GP24
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Bit 3
: PIN88S = 0 IRRX = 1 GP25 Bit 2 : PIN87S = 0 IRTX = 1 GP26 Bit 1 - 0 :PIN2S = 00 DRVDEN1 = 01 SMI# = 10 IRQIN1 (select IRQ resource through CRF3 Bit 7 - 4 of Logical Device 8) = 11 GP27 CR2C (GPIO multiplexed pin selection register 3. VCC powered. Default 0bsss11111) Bit 7 : Multi-function selection bit for pin 91, 92, 98 -100, and 106 - 110. = 0 GP21 - 22, GP60 - 62, and GP51 - GP55 = 1 VID function The corresponding power on setting pin is GP57 (pin 102). Its value is latched on the rising edge of PWROK after VDD is on. Refer to CRF9and CRFA of Logical Device C for detailed description of VID function. Bit 6 - 5 : Multi-function selection bit for pin 112, 113, 115, 116, and 118 = 00 GP74-71 and GP70 = 01 Reserved = 10 Smart Card function = 11 Reserved The corresponding power on setting pin for bit 6 is GP70 (pin 118) and GP72 (pin 115) for bit5. Both values are latched on the rising edge of PWROK after VDD is on. If either bit 5or bit 6 is set to "1" after PWROK rising edge, these two bit can only be read. They can be written if powered on to select GP function initially and switch to Smard Card function. Bit 4-0 : Reserved CR2D (Default 0x00) Test Mode: Reserved for Winbond. CR2E (Default 0x00) Test Mode: Reserved for Winbond. CR2F (Default 0x00) Test Mode: Reserved for Winbond.
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13.2 Logical Device 0 (FDC)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x03, 0xf0 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select FDC I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x06 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4 : Reserved. Bit 3 - 0 : These bits select IRQ resource for FDC. CR74 (Default 0x02 if PNPCSV = 0 during POR, default 0x04 otherwise) Bit 7 - 3 : Reserved. Bit 2 - 0 : These bits select DRQ resource for FDC. = 0x00 DMA0 = 0x01 DMA1 = 0x02 DMA2 = 0x03 DMA3 = 0x04 - 0x07 No DMA active CRF0 (Default 0x0E) FDD Mode Register Bit 7 : FIPURDWN This bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0, DSKCHG, and WP. =0 The internal pull-up resistors of FDC are turned on.(Default) =1 The internal pull-up resistors of FDC are turned off. Bit 6 : INTVERTZ This bit determines the polarity of all FDD interface signals. =0 FDD interface signals are active low. =1 FDD interface signals are active high.
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: DRV2EN (PS2 mode only) When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A. Bit 4 : Swap Drive 0, 1 Mode = 0 No Swap (Default) = 1 Drive and Motor sel 0 and 1 are swapped. Bit 3 - 2 :Interface Mode = 11 AT Mode (Default) = 10 (Reserved) = 01 PS/2 = 00 Model 30 Bit 1 : FDC DMA Mode = 0 Burst Mode is enabled = 1 Non-Burst Mode (Default) Bit 0 : Floppy Mode = 0 Normal Floppy Mode (Default) = 1 Enhanced 3-mode FDD CRF1 (Default 0x00) Bit 7 - 6 : Boot Floppy = 00 FDD A = 01 FDD B = 10 FDD C = 11 FDD D Bit 5, 4 : Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 6. Bit 3 - 2 : Density Select = 00 Normal (Default) = 01 Normal = 10 1 ( Forced to logic 1) = 11 0 ( Forced to logic 0) Bit 1 : DISFDDWR = 0 Enable FDD write. = 1 Disable FDD write(forces pins WE, WD stay high). Bit 0 : SWWP = 0 Normal, use WP to determine whether the FDD is write protected or not. = 1 FDD is always write-protected.
Bit 5
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CRF2 (Default 0xFF) Bit 7 - 6 : FDD D Drive Type Bit 5 - 4 : FDD C Drive Type Bit 3 - 2 : FDD B Drive Type Bit 1 - 0 : FDD A Drive Type CRF4 (Default 0x00) FDD0 Selection: Bit 7 : Reserved. Bit 6 : Precomp. Disable. = 1 Disable FDC Precompensation. = 0 Enable FDC Precompensation. Bit 5 : Reserved. Bit 4 - 3 : DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A). = 00 Select Regular drives and 2.88 format = 01 3-mode drive = 10 2 Meg Tape = 11 Reserved Bit 2 : Reserved. Bit 1:0 : DTYPE0, DTYPE1: Drive Type select (Refer to TABLE B). CRF5 (Default 0x00) FDD1 Selection: Same as FDD0 of CRF4.
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TABLE A Drive Rate Table Select DRTS1 DRTS0 0 0 Data Rate DRATE1 1 0 0 1 1 0 0 1 1 0 0 1 DRATE0 1 0 1 0 1 0 1 0 1 0 1 0 Selected Data Rate MFM 1Meg 500K 300K 250K 1Meg 500K 500K 250K 1Meg 500K 2Meg 250K FM --250K 150K 125K --250K 250K 125K --250K --125K SELDEN
0
1
1
0
1 1 0 0 1 1 0 0 1 1 0 0
TABLE B DTYPE0 0 DTYPE1 0 DRVDEN0(pin 2) SELDEN DRVDEN1(pin 3) DRATE0 DRIVE TYPE 4/2/1 MB 3.5"" 2/1 MB 5.25" 2/1.6/1 MB 3.5" (3-MODE)
0 1 1
1 0 1
DRATE1 SELDEN DRATE0
DRATE0 DRATE0 DRATE1
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13.3 Logical Device 1 (Parallel Port)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive.
CR60, CR 61 (Default 0x03, 0x78 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Parallel Port I/O base address. [0x100:0xFFC] on 4 byte boundary (EPP not supported) or [0x100:0xFF8] on 8 byte boundary (all modes supported, EPP is only available when the base address is on 8 byte boundary). CR70 (Default 0x07 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4 : Reserved. Bit [3:0] : These bits select IRQ resource for Parallel Port. CR74 (Default 0x03) Bit 7 - 3 : Reserved. Bit 2 - 0 : These bits select DRQ resource for Parallel Port. 0x00=DMA0 0x01=DMA1 0x02=DMA2 0x03=DMA3 0x04 - 0x07= No DMA active CRF0 (Default 0x3F) Bit 7 : Reserved. Bit 6 - 3 : ECP FIFO Threshold. Bit 2 - 0 : Parallel Port Mode (CR28 PRTMODS2 = 0) = 100 Printer Mode (Default) = 000 Standard and Bi-direction (SPP) mode = 001 EPP - 1.9 and SPP mode = 101 EPP - 1.7 and SPP mode = 010 ECP mode = 011 ECP and EPP - 1.9 mode = 111 ECP and EPP - 1.7 mode.
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13.4 Logical Device 2 (UART A)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1 : Reserved. Bit 0 : = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x03, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Serial Port 1 I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x04 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4 : Reserved. Bit 3 - 0 : These bits select IRQ resource for Serial Port 1. CRF0 (Default 0x00) Bit 7 - 2 : Reserved. Bit 1 - 0 : SUACLKB1, SUACLKB0 = 00 UART A clock source is 1.8462 MHz (24MHz/13) = 01 UART A clock source is 2 MHz (24MHz/12) = 10 UART A clock source is 24 MHz (24MHz/1) = 11 UART A clock source is 14.769 MHz (24MHz/1.625)
13.5 Logical Device 3 (UART B)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x02, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Serial Port 2 I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x03 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4 : Reserved. Bit [3:0] : These bits select IRQ resource for Serial Port 2.
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CRF0 (Default 0x00) Bit 7 - 4 : Reserved. Bit 3 : RXW4C = 0 No reception delay when SIR is changed from TX mode to RX mode. = 1 Reception delays 4 characters-time (40 bit-time) when SIR is changed from TX mode to RX mode. Bit 2 : TXW4C = 0 No transmission delay when SIR is changed from RX mode to TX mode. = 1 Transmission delays 4 characters-time (40 bit-time) when SIR is changed from RX mode to TX mode. Bit 1 - 0 : SUBCLKB1, SUBCLKB0 = 00 UART B clock source is 1.8462 Mhz (24MHz/13) = 01 UART B clock source is 2 Mhz (24MHz/12) = 10 UART B clock source is 24 Mhz (24MHz/1) = 11 UART B clock source is 14.769 Mhz (24mhz/1.625) CRF1 (Default 0x00) Bit 7 : Reserved. Bit 6 : IRLOCSEL. IR I/O pins' location select. = 0 Through SINB/SOUTB. = 1 Through IRRX/IRTX. Bit 5 : IRMODE2. IR function mode selection bit 2. Bit 4 : IRMODE1. IR function mode selection bit 1. Bit 3 : IRMODE0. IR function mode selection bit 0. IR MODE 00X 010* 011* 100 101 110 111* IR FUNCTION Disable IrDA IrDA ASK-IR ASK-IR ASK-IR ASK-IR IRTX tri-state Active pulse 1.6 S Active pulse 3/16 bit time Inverting IRTX/SOUTB pin Inverting IRTX/SOUTB & 500 KHZ clock Inverting IRTX/SOUTB Inverting IRTX/SOUTB & 500 KHZ clock IRRX high Demodulation into SINB/IRRX Demodulation into SINB/IRRX routed to SINB/IRRX routed to SINB/IRRX Demodulation into SINB/IRRX Demodulation into SINB/IRRX
Note: The notation is normal mode in the IR function.
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Bit 2 : HDUPLX. IR half/full duplex function select. = 0 The IR function is Full Duplex. = 1 The IR function is Half Duplex. : TX2INV. = 0 the SOUTB pin of UART B function or IRTX pin of IR function in normal condition. = 1 inverse the SOUTB pin of UART B function or IRTX pin of IR function. : RX2INV. = 0 the SINB pin of UART B function or IRRX pin of IR function in normal condition. = 1 inverse the SINB pin of UART B function or IRRX pin of IR function
Bit 1
Bit 0
13.6 Logical Device 5 (KBC)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x00, 0x60 if PNPCSV = 0 during POR, default 0x00 otherwise) These two registers select the first KBC I/O base address [0x100:0xFFF] on 1 byte boundary. CR62, CR 63 (Default 0x00, 0x64 if PNPCSV = 0 during POR, default 0x00 otherwise) These two registers select the second KBC I/O base address [0x100:0xFFF] on 1 byte boundary. CR70 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4 : Reserved. Bit [3:0] These bits select IRQ resource for KINT (keyboard). CR72 (Default 0x0C if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4 : Reserved. Bit [3:0] These bits select IRQ resource for MINT (PS2 Mouse)
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CRF0 (Default 0x80) Bit 7 - 6 : KBC clock rate selection = 00 Select 6MHz as KBC clock input. = 01 Select 8MHz as KBC clock input. = 10 Select 12Mhz as KBC clock input. = 11 Select 16Mhz as KBC clock input. (W83627SF/W83627HF/F-AW can support these 4 kinds of clock input, but W83627SF/ W83627HF/F-PW only support 12MHz clock input) Bit 5 - 3 : Reserved. Bit 2 = 0 Port 92 disable. = 1 Port 92 enable. Bit 1 = 0 Gate20 software control. = 1 Gate20 hardware speed up. Bit 0 = 0 KBRST software control. = 1 KBRST hardware speed up.
13.7 Logical Device 6 (CIR)
CR30 (Default 0x00) Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x00, 0x00) These two registers select CIR I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x00) Bit 7 - 4 : Reserved. Bit [3:0] These bits select IRQ resource for CIR.
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13.8 Logical Device 7 (Game Port and MIDI Port and GPIO Port 1)
CR30 (Default 0x00) Bit 7 - 3 : Reserved. Bit 2 = 1 Activate MIDI Port. = 0 MIDI Port is disabled if bit 0 is also 0. Bit 1 = 1 Activate Game Port. = 0 Game Port is is disabled if bit 0 is also 0. Bit 0 = 1 Activate both Game Port and MIDI Port. = 0 Game Port is disabled is bit1 is also 0. MIDI Port is disabled if bit2 is also 0. CR60, CR 61 (Default 0x02, 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) These two registers select the Game Port base address [0x100:0xFFF] on 1 byte boundary. CR62, CR 63 (Default 0x03, 0x30 if PNPCSV = 0 during POR, default 0x00 otherwise) These two registers select the MIDI Port base address [0x100:0xFFF] on 2 byte boundary. CR70 (Default 0x09 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4 : Reserved. Bit [3:0] : These bits select IRQ resource for MIDI Port . CRF0 (GP10-GP17 I/O selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP10-GP17 data register. Default 0x00) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP10-GP17 inversion register. Default 0x00) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register.
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CRF3 (MIDI FIFO Threshold register. Default 0x00) Bit 7 - 6: MIDI FIFO Threshold. BIT 7 0 0 1 1 Bit 5-0: Reserved BIT 6 0 1 0 1 RX FIFO INTERRUPT ACTIVE LEVEL (BYTES) 01 04 08 14
13.9 Logical Device 8 (GPIO Port 2)
CR30 (GP20-GP27 Default 0x00) Bit 7 - 1 : Reserved. Bit 0 = 1 Activate GPIO2. = 0 GPIO2 is inactive. note: bit 0 is initialized to power on setting value of pin 81 on the rising edge of PWROK. CR60, CR 61 (Default 0x00, 0x00) These two registers select GP2 I/O base address [0x100:0xFF8] on 1 byte boundary. CRF0 (GP20-GP27 I/O selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP20-GP27 data register. Default 0x00) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP20-GP27 inversion register. Default 0x00) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. CRF3 (Default 0x00) Bit 7 - 4 : These bits select IRQ resource for IRQIN1. Bit 3 - 0 : These bits select IRQ resource for IRQIN0. CRF4 (Reserved)
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CRF5 (PLED mode register. Default 0x00) Bit 7-6 : select PLED mode = 00 Power LED pin is tri-stated. = 01 Power LED pin is drived low. = 10 Power LED pin is a 1Hz toggle pulse with 50 duty cycle. = 11 Power LED pin is a 1/4Hz toggle pulse with 50 duty cycle. Bit 5-4 : Reserved Bit 3 : select WDTO count mode. =0 second =1 minute Bit 2 : Enable the rising edge of keyboard Reset(P20) to force Time-out event. = 0 Disable = 1 Enable Bit 1 : Enable the keyboard Reset output Low pluse when Time-out. = 0 Disable = 1 Enable Bit 0 : Reserved CRF6 (Default 0x00 if ENGMTO is 0, 0x0A if ENGMTO is 1) Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load the value to Watch Dog Counter and start counting down. If the Bit 7 and Bit 6 are set, any Mouse Interrupt or Keyboard Interrupt event will also cause the reload of previously-loaded non-zero value to Watch Dog Counter and start counting down. Reading this register returns current value in Watch Dog Counter instead of Watch Dog Timer Time-out value. Bit 7 - 0 = 0x00 Time-out Disable = 0x01 Time-out occurs after 1 second/minute = 0x02 Time-out occurs after 2 second/minutes = 0x03 Time-out occurs after 3 second/minutes ................................................ = 0xFF Time-out occurs after 255 second/minutes note: The corresponding power on setting pin is pin 81 and its value is latched on the rising edge of PWROK. 1: CRF6 is initialized to be 0x0A and CR30 of this logical device is initialized to be 0x01. 0: CRF6 is initialized to be 0x00 and CR30 of this logical device is initialized to be 0x00.
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CRF7 (Default 0x00) Bit 7 : Mouse interrupt reset Enable or Disable = 1 Watch Dog Timer is reset upon a Mouse interrupt = 0 Watch Dog Timer is not affected by Mouse interrupt Bit 6 : Keyboard interrupt reset Enable or Disable = 1 Watch Dog Timer is reset upon a Keyboard interrupt = 0 Watch Dog Timer is not affected by Keyboard interrupt Bit 5 : Force Watch Dog Timer Time-out, Write only* = 1 Force Watch Dog Timer time-out event; this bit is self-clearing. Bit 4 : Watch Dog Timer Status, R/W = 1 Watch Dog Timer time-out occurred. = 0 Watch Dog Timer counting Bit 3 -0 : These bits select IRQ resource for Watch Dog. Setting of 2 selects SMI.
13.10 Logical Device 9 (GPIO Port 3,4 are powered by standby source VSB)
CR30 (Default 0x02) Bit 7 - 1 : Reserved. Bit 1 = 1 Activate GP4. = 0 GP4 is inactive. Bit 0 = 1 Activate GPIO3. = 0 GPIO3 is inactive. CR60, CR 61 (Default 0x02, 0x90 if PNPCSV = 0 during POR, default 0x00 otherwise) These two registers select the GP3, GP4 port base address [0x100:0xFFF] on 2 byte boundary. GP3 is accessible through "base address" and GP4 is accessible through "base address" +1. CRF0 (GP30-GP35 I/O selection register. Default 0xFF Bit 7 - 6: Reserved) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP30-GP35 data register. Default 0x00 Bit 7 - 6: Reserved) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP30-GP35 inversion register. Default 0x00 Bit 7 - 6: Reserved) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register.
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CRF3 (SUSLED mode register. Default 0x00) Bit 7 - 6 : select Suspend LED mode = 00 Suspend LED pin is drived low. = 01 Suspend LED pin is tri-stated. = 10 Suspend LED pin is a 1 Hz toggle pulse with 50 duty cycle. = 11 Suspend LED pin is a 1/4 Hz toggle pulse with 50 duty cycle. Bit 5 - 0 : Reserved. CRF4 (GP40-GP42 I/O selection register. Default 0x00 Bit 7 - 3: Reserved) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF5 (GP40-GP42 data register. Default 0x00 Bit 7 - 3: Reserved) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF6 (GP40-GP42 inversion register. Default 0x00 Bit 7 - 3: Reserved) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register.
13.11 Logical Device A (ACPI)
CR30 (Default 0x00) Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive. CR70 (Default 0x00) Bit 7 - 4 : Reserved. Bit 3 - 0 : These bits select IRQ resources for PME .
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PRELIMINARY
CRE0 (Default 0x00) Bit 7 : DIS-PANSW_IN. Disable panel switch input to turn system power supply on. = 0 PANSW_IN is wire-ANDed and connected to PANSW_OUT. = 1 PANSW_IN is blocked and can not affect PANSW_OUT. Bit 6 : ENKBWAKEUP. Enable keyboard to wake up system through PANSW_OUT. = 0 Disable Keyboard wake-up function. = 1 Enable Keyboard wake-up function. Bit 5 : ENMSWAKEUP. Enable Mouse to wake-up system via PANSW_OUT. = 0 Disable Mouse wake-up function. = 1 Enable Mouse wake-up function. Bit 4 : MSRKEY. Select Mouse Left/Right Button to wake-up system via PANSW_OUT. = 0 Select click on Mouse Left-button twice to wake the system up. = 1 Select click on Mouse right-button twice to wake the system up. Bit 3 : ENCIRWAKEUP. Enable CIR to wake-up system via PANSW_OUT. =0 Disable CIR wake-up function. =1 Enable CIR wake-up function. Bit 2 : KB/MS Swap. Enable Keyboard/Mouse port-swap. = 0 Keyboard/Mouse ports are not swapped. = 1 Keyboard/Mouse ports are swapped. Bit 1 : MSXKEY. Enable any character received from Mouse to wake-up the system. = 0 Two clicks of Mouse left/right-button wakes up the system. =1 One click of Mouse left/right-button wakes up the system. Bit 0 : KBXKEY. Enable any character received from Keyboard to wake-up the system. = 0 Only predetermined specific key combination can wake up the system. = 1 Any character received from Keyboard can wake up the system.
CRE1 (Default 0x00) Keyboard Wake-Up Index Register This register is used to indicate which Keyboard Wake-Up Shift register or Predetermined key Register is to be read/written via CRE2. The first set of wake up key combination is in the range of 0x00 - 0x0E, the second set 0x30 - 0x3E, and the third set 0x40 - 0x4E. Incoming key combination can be read through 0x10 - 0x1E. The range of CIR wake-up index register is in 0x20 - 0x2F. CRE2 Keyboard Wake-Up Data Register This register holds the value of wake-up key register indicated by CRE1. This register can be read/written.
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PRELIMINARY
CRE3 (Read only. Keyboard/Mouse Wake-Up Status Register) Bit 7 - 6 : Reserved. Bit 5 : VSBLOSS: This bit is set when VSB is off. Bit 4 : PWRLOSS_STS: This bit is set when previous power state is off.. Bit 3 : CIR_STS. The Panel switch event is caused by CIR wake-up event. This bit is cleared by reading this register. Bit 2 : PANSW_STS. The Panel switch event is caused by PANSW_IN. This bit is cleared by reading this register. Bit 1 : Mouse_STS. The Panel switch event is caused by Mouse wake-up event. This bit is cleared by reading this register. Bit 0 : Keyboard_STS. The Panel switch event is caused by Keyboard wake-up event. This bit is cleared by reading this register. CRE4 (Default 0x00) Bit 7 : Power loss control bit 2. 0 = Disable ACPI resume. 1 = Enable ACPI resume. Bit 6 - 5 : Power loss control bit <1:0> 00 = System always turns off when come back from power loss state. 01 = System always turns on when come back from power loss state. 10 = System turns on/off when come back from power loss state depending on the state before power loss. 11 = Reserved. Bit 4 : Suspend clock source select 0 = Use internal clock source. 1 = Use external suspend clock source(32.768KHz). Bit 3 : Keyboard wake-up type select for wake-up the system from S1/S2. 0 = Password or Hot keys programmed in the registers. 1 = Any key. Bit 2 : Enable all wake-up event set in CRE0 can wake-up the system from S1/S2 state. This bit is cleared when wake-up event occurs. 0 = Disable. 1 = Enable. Bit 1 - 0 : Reserved.
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PRELIMINARY
CRE5 (Default 0x00) Bit 7 : ENS5RST: Enable S5# signal (pin 103) to reset SUSLED mode register (CRF3 of logical device 9). = 0 SUSLED mode register is reset only by RSMRST#. = 1 SUSLED mode register can be reset by RSMRST# or S5#. Bit 6 - 0 : Compared Code Length. When the compared codes are storaged in the data register, these data length should be written to this register. CRE6 (Default 0x00) Bit 7 : ENMDATUP: Enable an MDAT low pulse to wake up system through PSOUT#. = 0 Disable. = 1 Enable. Bit 6 : EN_SCUP: Enable SCPSNT# of Smart Card interface to wake up system through PSOUT#. = 0 Disable. = 1 Enable. Bit 5 - 0 : CIR Baud Rate Divisor. The clock base of CIR is 32k Hz, so that the baud rate is 32khz divided by (CIR Baud Rate Divisor + 1). CRE7 (Default 0x00) Bit 7 : ENKD3. Enable the third set of key combination to wake up system through PANSW_OUT if keyboard wake up function is enabled. = 0 Disable the third set of key combination. = 1 Enable the third set of key combination. Bit 6 : ENKD2. Enable the second set of key combination to wake up system through PANSW_OUT if keyboard wake up function is enabled. = 0 Disable the second set of key combination. = 1 Enable the second set of key combination. Bit 5 : ENWIN98KEY. Enable WIN98 keyboard dedicated key to wake up system through PANSW_OUT if keyboard wake up function is enabled. = 0 Disable WIN98 keyboard wake up. = 1 Enable WIN98 keyboard wake up. Bit 4 : EN_ONPSOUT. Enable to issue a 0.5 s long PSOUT# pulse when system returns from power loss state and is supposed to be on as described in CRE4 bit 6, 5 of logical device A. = 0 Disable this function. = 1 Enable this function.
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PRELIMINARY
Bit 3
Bit 2 Bit 1
Bit 0
: SELWDTORST: Select whether Watch Dog timer function is reset by LRESET_L signal or PWROK signal. = 0 Watch Dog timer function is reset by LRESET_L signal. = 1 Watch Dog timer function is reset by PWROK signal. : Reset CIR Power-On function. After using CIR power-on, the software should write logical 1 to restart CIR power-on function. : Invert RX Data. = 1 Inverting RX Data. = 0 Not inverting RX Data. : Enable Demodulation. = 1 Enable received signal to demodulate. = 0 Disable received signal to demodulate.
CRF0 (Default 0x00) Bit 7 : CHIPPME. Chip level auto power management enable. = 0 disable the auto power management functions = 1 enable the auto power management functions. Bit 6 : CIRPME. Consumer IR port auto power management enable. = 0 disable the auto power management functions = 1 enable the auto power management functions. Bit 5 : MIDIPME. MIDI port auto power management enable. = 0 disable the auto power management functions = 1 enable the auto power management functions. Bit 4 : SCPME. Smart Card interface auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions. Bit 3 : PRTPME. Printer port auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions. Bit 2 : FDCPME. FDC auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions. Bit 1 : URAPME. UART A auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions. Bit 0 : URBPME. UART B auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions.
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PRELIMINARY
CRF1 (Default 0x00) Bit 7 : WAK_STS. This bit is set when the chip is in the sleeping state and an enabled resume event occurs. Upon setting this bit, the sleeping/working state machine will transition the system to the working state. This bit is only set by hardware and is cleared by writing a 1 to this bit position or by the sleeping/working state machine automatically when the global standby timer expires. =0 the chip is in the sleeping state. =1 the chip is in the working state. Bit 6 - 0 : Devices' trap status. CRF3 (Default 0x00) Bit 7 - 6 : Reserved. Return zero when read. Bit 5 - 0 : Device's IRQ status. These bits indicate the IRQ status of the individual device respectively. The device's IRQ status bit is set by their source device and is cleared by writing a 1. Writing a 0 has no effect. Bit 5 : MOUIRQSTS. MOUSE IRQ status. Bit 4 : KBCIRQSTS. KBC IRQ status. Bit 3 : PRTIRQSTS. printer port IRQ status. Bit 2 : FDCIRQSTS. FDC IRQ status. Bit 1 : URAIRQSTS. UART A IRQ status. Bit 0 : URBIRQSTS. UART B IRQ status. CRF4 (Default 0x00) Bit 7 : Reserved. Return zero when read. Bit 4 - 0 : These bits indicate the IRQ status of the individual GPIO function or logical device respectively. The status bit is set by their source function or device and is cleared by writing a 1. Writing a 0 has no effect. Bit 6 : SCIRQSTS. Smart Card interface IRQ status. Bit 5 : Reserved. Return zero when read. Bit 4 : WDTIRQSTS. Watch dog timer IRQ status. Bit 3 : CIRIRQSTS. Consumer IR IRQ status. Bit 2 : MIDIIRQSTS. MIDI IRQ status. Bit 1 : IRQIN1STS. IRQIN1 status. Bit 0 : IRQIN0STS. IRQIN0 status.
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PRELIMINARY
CRF6 (Default 0x00) Bit 7 - 6 : Reserved. Return zero when read. Bit 5 - 0 : Enable bits of the SMI / PME generation due to the device's IRQ. These bits enable the generation of an SMI / PME interrupt due to any IRQ of the devices. SMI / PME logic output = (MOUIRQEN and MOUIRQSTS) or (KBCIRQEN and KBCIRQSTS) or (PRTIRQEN and PRTIRQSTS) or (FDCIRQEN and FDCIRQSTS) or (URAIRQEN and URAIRQSTS) or (URBIRQEN and URBIRQSTS) or (SCIRQEN and SCIRQSTS) or (WDTIRQEN and WDTIRQSTS) or (IRQIN3EN and IRQIN3STS) or (IRQIN2EN and IRQIN2STS) or (IRQIN1EN and IRQIN1STS) or (IRQIN0EN and IRQIN0STS) Bit 5 : MOUIRQEN. = 0 disable the generation of an SMI / PME interrupt due to MOUSE's IRQ. Bit 4 = 1 enable the generation of an SMI / PME interrupt due to MOUSE's IRQ. : KBCIRQEN. = 0 disable the generation of an SMI / PME interrupt due to KBC's IRQ. Bit 3 = 1 enable the generation of an SMI / PME interrupt due to KBC's IRQ. : PRTIRQEN. = 0 disable the generation of an SMI / PME interrupt due to printer port's IRQ. Bit 2 = 1 enable the generation of an SMI / PME interrupt due to printer port's IRQ. : FDCIRQEN. = 0 disable the generation of an SMI / PME interrupt due to FDC's IRQ. Bit 1 = 1 enable the generation of an SMI / PME interrupt due to FDC's IRQ. : URAIRQEN. = 0 disable the generation of an SMI / PME interrupt due to UART A's IRQ. Bit 0 = 1 enable the generation of an SMI / PME interrupt due to UART A's IRQ. : URBIRQEN. = 0 disable the generation of an SMI / PME interrupt due to UART B's IRQ. = 1 enable the generation of an SMI / PME interrupt due to UART B's IRQ.
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PRELIMINARY
CRF7 (Default 0x00) Bit 7 : Reserved. Return zero when read. Bit 5 - 0 : Enable bits of the SMI / PME generation due to the GPIO IRQ function or device's IRQ. Bit 6 : SCIRQEN. = 0 disable the generation of an SMI / PME interrupt due to Smart Card interface IRQ. Bit 5 Bit 4 = 1 enable the generation of an SMI / PME interrupt due to Smart Card interface IRQ. : Reserved. Return zero when read. : WDTIRQEN. = 0 disable the generation of an SMI / PME interrupt due to watch dog timer's IRQ. Bit 3 = 1 enable the generation of an SMI / PME interrupt due to watch dog timer's IRQ. : CIRIRQEN. = 0 disable the generation of an SMI / PME interrupt due to CIR's IRQ. Bit 2 = 1 enable the generation of an SMI / PME interrupt due to CIR's IRQ. : MIDIIRQEN. = 0 disable the generation of an SMI / PME interrupt due to MIDI's IRQ. Bit 1 = 1 enable the generation of an SMI / PME interrupt due to MIDI's IRQ. : IRQIN1EN. = 0 disable the generation of an SMI / PME interrupt due to IRQIN1's IRQ. Bit 0 = 1 enable the generation of an SMI / PME interrupt due to IRQIN1's IRQ. : IRQIN0EN. = 0 disable the generation of an SMI / PME interrupt due to IRQIN0's IRQ. = 1 enable the generation of an SMI / PME interrupt due to IRQIN0's IRQ. CRF9 (Default 0x00) Bit 7 - 3: Reserved. Return zero when read. Bit 2 : PME_EN: Select the power management events to be either an PME or SMI interrupt for the IRQ events. Note that: this bit is valid only when SMIPME_OE = 1. =0 Bit 1 the power management events will generate an SMI event. =1 the power management events will generate an PME event. : FSLEEP: This bit selects the fast expiry time of individual devices. =0 1 second. =1 8 milli-seconds. : SMIPME_OE: This is the SMI and PME output enable bit. =0 =1 neither SMI nor PME will be generated. Only the IRQ status bit is set. an SMI or PME event will be generated.
Bit 0
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PRELIMINARY
CRFE, FF (Default 0x00) Reserved for Winbond test.
13.12 Logical Device B (Smart Card interface)
CR30 (Default 0x00) Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x00, 0x00) These two registers select Smart Card interface base address [0x100:0xFFF] on 8-byte boundary. CR70 (Default 0x00) Bit 7 - 4 : Reserved. Bit 3 - 0 : These bits select IRQ resource for Smart Card interface.
13.13 Logical Device C (GPIO Port 5,6,7 This power of the Ports is Source VCC)
CR30 (Default 0x07) Bit 7 - 3 : Reserved. Bit 2 = 1 Activate GP7. = 0 GP7 is inactive. Bit 1 = 1 Activate GP6. = 0 GP6 is inactive. Bit 0 = 1 Activate GP5 = 0 GP5 is inactive. CR60, CR 61 (Default 0x00) These two registers select the GP5, GP6, GP7 port base address [0x100:0xFFF] on 4 byte boundary. GP5 is accessible through "base address", GP6 "base address" +1, and GP7 "base address" +2. CRF0 (GP50-GP56 I/O selection register. Default 0x00 Bit 7: Reserved) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port.
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PRELIMINARY
CRF1 (GP50-GP56 data register. Default 0x00 Bit 7: Reserved) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP50-GP56 inversion register. Default 0x00 Bit 7: Reserved) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. CRF3 (GP60-GP63 I/O selection register. Default 0xFF Bit 7-4: Reserved) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF4 (GP60-GP63 data register. Default 0xFF Bit 7-4: Reserved) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF5 (GP60-GP63 inversion register. Default 0x00 Bit 7-4: Reserved) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. CRF6 (GP70-GP74 I/O selection register. Default 0xFF Bit 7-5: Reserved) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF7 (GP70-GP74 data register. Default 0xFF Bit 7-5: Reserved) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF8 (GP70-GP74 inversion register. Default 0x00 Bit 7-5: Reserved) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. CRF9 (VID input data register. Bit 7 - 5: Reserved) This register is read only. It contains original VID value. Bit 7 - 5 : Reserved. Bit 4 - 0 : Original VID value.
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PRELIMINARY
CRFA (VID output data register) This register allows user to configure different VID value. It can be read or written. Bit 7 : Select VID code tables. = 0 old VID code table. = 1 new VID code table. Bit 6 - 5 : VID guarding bits. The corresponding power on setting pins are GP56, 66 and their values are latched on the rising edge of PWROK signal. Bit 6 0 0 1 1 Bit 5 Limit 0 No constraint 1 3 units constraint 0 4 units constraint 1 5 units constraint
Bit 4 - 0 : configurable VID output value. If VIDSEL of CR2C is 1 (select VID function), GP22, 21, 62 - 60 function as VID inputs and 55 - 51 function as VID outputs. During PWROK = 0, GP55~51 (VIDOUT) are equivalent to GP22, 21, 62~60 (VIDIN). After power on, User may configure LC.CRFA.bit4 - 0 to output a new VIDOUT combination if this new combination comply with the constraints of VID guarding bits specified in bit 6, 5 of this register. VID outputs are equal to VID inputs if constraint is not met.
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PRELIMINARY 14. SPECIFICATIONS
14.1 Absolute Maximum Ratings
PARAMETER Power Supply Voltage (5V) Input Voltage RTC Battery Voltage VBAT Operating Temperature Storage Temperature RATING -0.5 to 7.0 -0.5 to VDD+0.5 2.2 to 4.0 0 to +70 -55 to +150 UNIT V V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
14.2 DC CHARACTERISTICS
(Ta = 0 C to 70 C, VDD = 5V 10%, VSS = 0V) PARAMETER RTC Battery Quiescent Current ACPI Stand-by Power Supply Quiescent Current SYM. IBAT IBAT MIN. TYP. MAX. 2.4 2.0 UNIT uA mA CONDITIONS VBAT = 2.5 V VSB = 5.0 V, All ACPI pins are not connected.
I/O8t - TTL level bi-directional pin with source-sink capability of 8 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V A A IOL = 8 mA IOH = - 8 mA VIN = VDD VIN = 0V
I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V A A IOL = 12 mA IOH = -12 mA VIN = VDD VIN = 0V
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PRELIMINARY
14.2 DC CHARACTERISTICS, continued PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS I/O12tp3 - 3.3 V TTL level bi-directional pin with source-sink capability of 12 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V A A IOL = 12 mA IOH = -12 mA VIN = 3.3V VIN = 0V
I/OD12t - TTL level bi-directional pin with sink capability of 12 mA and open-drain Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage VIL VIH VOL ILIH ILIL 2.0 0.4 +10 -10 0.8 V V V A A IOL = 12 mA VIN = 3.3V VIN = 0V
I/O24t - TTL level bi-directional pin with source-sink capability of 24 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V A A IOL = 24 mA IOH = -24 mA VIN = VDD VIN = 0V
OUT12t - TTL level output pin with source-sink capability of 12 mA Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 V V IOL = 12 mA IOH = -12 mA
OUT12tp3 - 3.3 V TTL level output pin with source-sink capability of 12 mA Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 V V IOL = 12 mA IOH = -12 mA
OD12 - Open-drain output pin with sink capability of 12 mA Output Low Voltage VOL 0.4 V IOL = 12 mA OD24 - Open-drain output pin with sink capability of 24 mA Output Low Voltage VOL 0.4 V IOL = 24 mA
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PRELIMINARY
14.2 DC CHARACTERISTICS, continued PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS
INtd - TTL level input pin with internal pull down resistor Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage pull down resistor INt - TTL level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 2.0 +10 -10 0.8 V V A A VIN = VDD VIN = 0 V VIL VIH ILIH ILIL R 2.0 +10 -10 47 0.8 V V A A K VIN = VDD VIN = 0 V
INcs - CMOS level Schmitt-triggered input pin Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage VtVt+ VTH ILIH ILIL 1.3 3.2 1.5 1.5 3.5 2 +10 -10 1.7 3.8 V V V A A VDD = 5 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V
INts - TTL level Schmitt-triggered input pin Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage INtsp3 VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 +10 -10 1.1 2.4 V V V A A VDD = 5 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V
- 3.3 V TTL level Schmitt-triggered input pin VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 +10 -10 1.1 2.4 V V V A A VDD = 3.3 V VDD = 3.3 V VDD = 3.3 V VIN = 3.3 V VIN = 0 V
Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage
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PRELIMINARY 15. APPLICATION CIRCUITS
15.1 Parallel Port Extension FDD
JP13
WE2/SLCT WD2/PE MOB2/BUSY DSB2/ACK PD7 PD6 PD5 DCH2/PD4 RDD2/PD3 STEP2/SLIN WP2/PD2 DIR2/INIT TRK02/PD1 HEAD2/ERR IDX2/PD0 RWC2/AFD STB 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1
JP 13A
DCH2 HEAD2 RDD2
WP2
TRK02 WE2 WD2 STEP2 DIR2 MOB2 DSB2 IDX2
RWC2
34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
EXT FDC
PRINTER PORT
Parallel Port Extension FDD Mode Connection Diagram
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PRELIMINARY
15.2 Parallel Port Extension 2FDD
JP13
WE2/SLCT WD2/PE MOB2/BUSY DSB2/ACK DSA2/PD7 MOA2/PD6 PD5 DCH2/PD4 RDD2/PD3 STEP2/SLIN WP2/PD2 DIR2/INIT TRK02/PD1 HEAD2/ERR IDX2/PD0 RWC2/AFD STB 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1
JP 13A
DCH2 HEAD2 RDD2
WP2
TRK02 WE2 WD2 STEP2 DIR2 MOB2 DSA2 DSB2 MOA2 IDX2
RWC2
34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
EXT FDC
PRINTER PORT
Parallel Port Extension 2FDD Connection Diagram
15.3 Four FDD Mode
74LS139 W83977F DSA DSB MOA MOB G2 A2 B2 G1 A1 B1 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 DSA DSB DSC DSD MOA MOB MOC MOD 7407(2)
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PRELIMINARY 16. ORDERING INSTRUCTION
PART NO. W83627SF-AW W83627SF-PW KBC FIRMWARE AMIKEY-2
TM TM
REMARKS
Phoenix MultiKey/42
Only support 12MHz KBC clock input
17. HOW TO READ THE TOP MARKING
Example: The top marking of W83627SF-AW
inbond
W83627SF-AW
(c) AM. MEGA. 87-96 821A2B282012345
1st line: Winbond logo 2nd line: the type number: W83627SF-AW 3rd line: the source of KBC F/W -- American Megatrends Incorporated 4th line: the tracking code 821 A 2 C 282012345 821: packages made in '98, week 21 A: assembly house ID; A means ASE, S means SPIL.... etc. 2: Winbond internal use. B: IC revision; A means version A, B means version B 282012345: wafer production series lot number
TM
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PRELIMINARY 18. PACKAGE DIMENSIONS
(128-pin QFP)
HE E
128 103
Symbol
Dimension in inch
Dimension in mm
Min
0.25 2.57 0.10 0.10 13.90 19.90 17.00 23.00 0.65
Nom Max
0.35 2.72 0.20 0.15 14.00 20.00 0.50 17.20 23.20 0.80 1.60 0.08 7 17.40 23.40 0.95 0.45 2.87 0.30 0.20 14.10 20.10
Min
0.010 0.101 0.004 0.004 0.547 0.783 0.669 0.905 0.025
Nom Max
0.014 0.107 0.008 0.006 0.551 0.787 0.020 0.677 0.913 0.031 0.063 0.003 0.685 0.921 0.037 0.018 0.113 0.012 0.008 0.555 0.791
1
102
D
HD
38
65
39
e
b
64
A1 A2 b c D E e HD HE L L1 y 0
c
0
0
7
Note:
1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion . 3.Controlling dimension : Millimeter 4.General appearance spec. should be based on final visual inspection spec.
A A2 See Detail F Seating Plane A1
y
L L1 Detail F
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
Note: All data and specifications are subject to change without notice.
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